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Merge tag 'mtk-soc-for-v7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/drivers

Browse Source 
MediaTek SoC driver updates

This adds a fix for a missing error check in mtk-socinfo, and
also a missing MODULE_DEVICE_TABLE() in the mtk-dvfsrc driver.

Besides from that, this also reworks how the MMSYS tables are
specified with the macro, separating the component's hardware
instance from the actual type, resolving a prerequirement for
the restructuring of mediatek-drm.

* tag 'mtk-soc-for-v7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux:
  soc: mediatek: add missing MODULE_DEVICE_TABLE()
  soc: mediatek: mtk-mmsys: Use MMSYS_ROUTE() in default routing table
  soc: mediatek: mtk-mmsys: Rework routes to specify component ID
  soc: mediatek: mtk-socinfo Add error handling in devm_kasprintf()

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2026-07-30 11:21:45 +02:00
parent ce9af94e6d ec76205786
commit aa469c0c55
11 changed files with 321 additions and 360 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
drivers/soc/mediatek/mt8167-mmsys.h
View File

@@ -19,19 +19,19 @@
#define MT8167_DSI0_SEL_IN_MASK 0x3
static const struct mtk_mmsys_routes mt8167_mmsys_routing_table[] = {
MMSYS_ROUTE(OVL0, COLOR0,
MMSYS_ROUTE(OVL, 0, COLOR, 0,
MT8167_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_COLOR0,
OVL0_MOUT_EN_COLOR0),
MMSYS_ROUTE(DITHER0, RDMA0,
MMSYS_ROUTE(DITHER, 0, RDMA, 0,
MT8167_DISP_REG_CONFIG_DISP_DITHER_MOUT_EN, MT8167_DITHER_MOUT_EN_MASK,
MT8167_DITHER_MOUT_EN_RDMA0),
MMSYS_ROUTE(OVL0, COLOR0,
MMSYS_ROUTE(OVL, 0, COLOR, 0,
MT8167_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, COLOR0_SEL_IN_OVL0,
COLOR0_SEL_IN_OVL0),
MMSYS_ROUTE(RDMA0, DSI0,
MMSYS_ROUTE(RDMA, 0, DSI, 0,
MT8167_DISP_REG_CONFIG_DISP_DSI0_SEL_IN, MT8167_DSI0_SEL_IN_MASK,
MT8167_DSI0_SEL_IN_RDMA0),
MMSYS_ROUTE(RDMA0, DSI0,
MMSYS_ROUTE(RDMA, 0, DSI, 0,
MT8167_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN, MT8167_RDMA0_SOUT_MASK,
MT8167_RDMA0_SOUT_DSI0),
};

28
drivers/soc/mediatek/mt8173-mmsys.h
View File

@@ -33,46 +33,46 @@
#define MT8173_RDMA0_SOUT_COLOR0 BIT(0)
static const struct mtk_mmsys_routes mt8173_mmsys_routing_table[] = {
MMSYS_ROUTE(OVL0, COLOR0,
MMSYS_ROUTE(OVL, 0, COLOR, 0,
MT8173_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, MT8173_OVL0_MOUT_EN_COLOR0,
MT8173_OVL0_MOUT_EN_COLOR0),
MMSYS_ROUTE(OD0, RDMA0,
MMSYS_ROUTE(OD, 0, RDMA, 0,
MT8173_DISP_REG_CONFIG_DISP_OD_MOUT_EN, MT8173_OD0_MOUT_EN_RDMA0,
MT8173_OD0_MOUT_EN_RDMA0),
MMSYS_ROUTE(UFOE, DSI0,
MMSYS_ROUTE(UFOE, 0, DSI, 0,
MT8173_DISP_REG_CONFIG_DISP_UFOE_MOUT_EN, MT8173_UFOE_MOUT_EN_DSI0,
MT8173_UFOE_MOUT_EN_DSI0),
MMSYS_ROUTE(COLOR0, AAL0,
MMSYS_ROUTE(COLOR, 0, AAL, 0,
MT8173_DISP_REG_CONFIG_DISP_COLOR0_SOUT_SEL_IN, MT8173_COLOR0_SOUT_MERGE,
0 /* SOUT to AAL */),
MMSYS_ROUTE(RDMA0, UFOE,
MMSYS_ROUTE(RDMA, 0, UFOE, 0,
MT8173_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL_IN, MT8173_RDMA0_SOUT_COLOR0,
0 /* SOUT to UFOE */),
MMSYS_ROUTE(OVL0, COLOR0,
MMSYS_ROUTE(OVL, 0, COLOR, 0,
MT8173_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, MT8173_COLOR0_SEL_IN_OVL0,
MT8173_COLOR0_SEL_IN_OVL0),
MMSYS_ROUTE(AAL0, COLOR0,
MMSYS_ROUTE(AAL, 0, COLOR, 0,
MT8173_DISP_REG_CONFIG_DISP_AAL_SEL_IN, MT8173_AAL_SEL_IN_MERGE,
0 /* SEL_IN from COLOR0 */),
MMSYS_ROUTE(RDMA0, UFOE,
MMSYS_ROUTE(RDMA, 0, UFOE, 0,
MT8173_DISP_REG_CONFIG_DISP_UFOE_SEL_IN, MT8173_UFOE_SEL_IN_RDMA0,
0 /* SEL_IN from RDMA0 */),
MMSYS_ROUTE(UFOE, DSI0,
MMSYS_ROUTE(UFOE, 0, DSI, 0,
MT8173_DISP_REG_CONFIG_DSI0_SEL_IN, MT8173_DSI0_SEL_IN_UFOE,
0 /* SEL_IN from UFOE */),
MMSYS_ROUTE(OVL1, COLOR1,
MMSYS_ROUTE(OVL, 1, COLOR, 1,
MT8173_DISP_REG_CONFIG_DISP_OVL1_MOUT_EN, MT8173_OVL1_MOUT_EN_COLOR1,
MT8173_OVL1_MOUT_EN_COLOR1),
MMSYS_ROUTE(GAMMA, RDMA1,
MMSYS_ROUTE(GAMMA, 0, RDMA, 1,
MT8173_DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN, MT8173_GAMMA_MOUT_EN_RDMA1,
MT8173_GAMMA_MOUT_EN_RDMA1),
MMSYS_ROUTE(RDMA1, DPI0,
MMSYS_ROUTE(RDMA, 1, DPI, 0,
MT8173_DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
RDMA1_SOUT_DPI0),
MMSYS_ROUTE(OVL1, COLOR1,
MMSYS_ROUTE(OVL, 1, COLOR, 1,
MT8173_DISP_REG_CONFIG_DISP_COLOR1_SEL_IN, COLOR1_SEL_IN_OVL1,
COLOR1_SEL_IN_OVL1),
MMSYS_ROUTE(RDMA1, DPI0,
MMSYS_ROUTE(RDMA, 1, DPI, 0,
MT8173_DISP_REG_CONFIG_DPI_SEL_IN, MT8173_DPI0_SEL_IN_MASK,
MT8173_DPI0_SEL_IN_RDMA1),
};

14
drivers/soc/mediatek/mt8183-mmsys.h
View File

@@ -28,25 +28,25 @@
#define MT8183_MMSYS_SW0_RST_B 0x140
static const struct mtk_mmsys_routes mmsys_mt8183_routing_table[] = {
MMSYS_ROUTE(OVL0, OVL_2L0,
MMSYS_ROUTE(OVL, 0, OVL_2L, 0,
MT8183_DISP_OVL0_MOUT_EN, MT8183_OVL0_MOUT_EN_OVL0_2L,
MT8183_OVL0_MOUT_EN_OVL0_2L),
MMSYS_ROUTE(OVL_2L0, RDMA0,
MMSYS_ROUTE(OVL_2L, 0, RDMA, 0,
MT8183_DISP_OVL0_2L_MOUT_EN, MT8183_OVL0_2L_MOUT_EN_DISP_PATH0,
MT8183_OVL0_2L_MOUT_EN_DISP_PATH0),
MMSYS_ROUTE(OVL_2L1, RDMA1,
MMSYS_ROUTE(OVL_2L, 1, RDMA, 1,
MT8183_DISP_OVL1_2L_MOUT_EN, MT8183_OVL1_2L_MOUT_EN_RDMA1,
MT8183_OVL1_2L_MOUT_EN_RDMA1),
MMSYS_ROUTE(DITHER0, DSI0,
MMSYS_ROUTE(DITHER, 0, DSI, 0,
MT8183_DISP_DITHER0_MOUT_EN, MT8183_DITHER0_MOUT_IN_DSI0,
MT8183_DITHER0_MOUT_IN_DSI0),
MMSYS_ROUTE(OVL_2L0, RDMA0,
MMSYS_ROUTE(OVL_2L, 0, RDMA, 0,
MT8183_DISP_PATH0_SEL_IN, MT8183_DISP_PATH0_SEL_IN_OVL0_2L,
MT8183_DISP_PATH0_SEL_IN_OVL0_2L),
MMSYS_ROUTE(RDMA1, DPI0,
MMSYS_ROUTE(RDMA, 1, DPI, 0,
MT8183_DISP_DPI0_SEL_IN, MT8183_DPI0_SEL_IN_RDMA1,
MT8183_DPI0_SEL_IN_RDMA1),
MMSYS_ROUTE(RDMA0, COLOR0,
MMSYS_ROUTE(RDMA, 0, COLOR, 0,
MT8183_DISP_RDMA0_SOUT_SEL_IN, MT8183_RDMA0_SOUT_COLOR0,
MT8183_RDMA0_SOUT_COLOR0),
};

22
drivers/soc/mediatek/mt8186-mmsys.h
View File

@@ -63,37 +63,37 @@
#define MT8186_MMSYS_SW0_RST_B 0x160
static const struct mtk_mmsys_routes mmsys_mt8186_routing_table[] = {
MMSYS_ROUTE(OVL0, RDMA0,
MMSYS_ROUTE(OVL, 0, RDMA, 0,
MT8186_DISP_OVL0_MOUT_EN, MT8186_OVL0_MOUT_EN_MASK,
MT8186_OVL0_MOUT_TO_RDMA0),
MMSYS_ROUTE(OVL0, RDMA0,
MMSYS_ROUTE(OVL, 0, RDMA, 0,
MT8186_DISP_RDMA0_SEL_IN, MT8186_RDMA0_SEL_IN_MASK,
MT8186_RDMA0_FROM_OVL0),
MMSYS_ROUTE(OVL0, RDMA0,
MMSYS_ROUTE(OVL, 0, RDMA, 0,
MT8186_MMSYS_OVL_CON, MT8186_MMSYS_OVL0_CON_MASK,
MT8186_OVL0_GO_BLEND),
MMSYS_ROUTE(RDMA0, COLOR0,
MMSYS_ROUTE(RDMA, 0, COLOR, 0,
MT8186_DISP_RDMA0_SOUT_SEL, MT8186_RDMA0_SOUT_SEL_MASK,
MT8186_RDMA0_SOUT_TO_COLOR0),
MMSYS_ROUTE(DITHER0, DSI0,
MMSYS_ROUTE(DITHER, 0, DSI, 0,
MT8186_DISP_DITHER0_MOUT_EN, MT8186_DITHER0_MOUT_EN_MASK,
MT8186_DITHER0_MOUT_TO_DSI0),
MMSYS_ROUTE(DITHER0, DSI0,
MMSYS_ROUTE(DITHER, 0, DSI, 0,
MT8186_DISP_DSI0_SEL_IN, MT8186_DSI0_SEL_IN_MASK,
MT8186_DSI0_FROM_DITHER0),
MMSYS_ROUTE(OVL_2L0, RDMA1,
MMSYS_ROUTE(OVL_2L, 0, RDMA, 1,
MT8186_DISP_OVL0_2L_MOUT_EN, MT8186_OVL0_2L_MOUT_EN_MASK,
MT8186_OVL0_2L_MOUT_TO_RDMA1),
MMSYS_ROUTE(OVL_2L0, RDMA1,
MMSYS_ROUTE(OVL_2L, 0, RDMA, 1,
MT8186_DISP_RDMA1_SEL_IN, MT8186_RDMA1_SEL_IN_MASK,
MT8186_RDMA1_FROM_OVL0_2L),
MMSYS_ROUTE(OVL_2L0, RDMA1,
MMSYS_ROUTE(OVL_2L, 0, RDMA, 1,
MT8186_MMSYS_OVL_CON, MT8186_MMSYS_OVL0_2L_CON_MASK,
MT8186_OVL0_2L_GO_BLEND),
MMSYS_ROUTE(RDMA1, DPI0,
MMSYS_ROUTE(RDMA, 1, DPI, 0,
MT8186_DISP_RDMA1_MOUT_EN, MT8186_RDMA1_MOUT_EN_MASK,
MT8186_RDMA1_MOUT_TO_DPI0_SEL),
MMSYS_ROUTE(RDMA1, DPI0,
MMSYS_ROUTE(RDMA, 1, DPI, 0,
MT8186_DISP_DPI0_SEL_IN, MT8186_DPI0_SEL_IN_MASK,
MT8186_DPI0_FROM_RDMA1),
};

78
drivers/soc/mediatek/mt8188-mmsys.h
View File

@@ -202,124 +202,124 @@ static const u8 mmsys_mt8188_vdo1_rst_tb[] = {
};
static const struct mtk_mmsys_routes mmsys_mt8188_routing_table[] = {
MMSYS_ROUTE(OVL0, RDMA0,
MMSYS_ROUTE(OVL, 0, RDMA, 0,
MT8188_VDO0_OVL_MOUT_EN, MT8188_MOUT_DISP_OVL0_TO_DISP_RDMA0,
MT8188_MOUT_DISP_OVL0_TO_DISP_RDMA0),
MMSYS_ROUTE(OVL0, WDMA0,
MMSYS_ROUTE(OVL, 0, WDMA, 0,
MT8188_VDO0_OVL_MOUT_EN, MT8188_MOUT_DISP_OVL0_TO_DISP_WDMA0,
MT8188_MOUT_DISP_OVL0_TO_DISP_WDMA0),
MMSYS_ROUTE(OVL0, RDMA0,
MMSYS_ROUTE(OVL, 0, RDMA, 0,
MT8188_VDO0_DISP_RDMA_SEL, MT8188_SEL_IN_DISP_RDMA0_FROM_MASK,
MT8188_SEL_IN_DISP_RDMA0_FROM_DISP_OVL0),
MMSYS_ROUTE(DITHER0, DSI0,
MMSYS_ROUTE(DITHER, 0, DSI, 0,
MT8188_VDO0_DSI0_SEL_IN, MT8188_SEL_IN_DSI0_FROM_MASK,
MT8188_SEL_IN_DSI0_FROM_DISP_DITHER0),
MMSYS_ROUTE(DITHER0, MERGE0,
MMSYS_ROUTE(DITHER, 0, MERGE, 0,
MT8188_VDO0_VPP_MERGE_SEL, MT8188_SEL_IN_VPP_MERGE_FROM_MASK,
MT8188_SEL_IN_DP_INTF0_FROM_DISP_DITHER0),
MMSYS_ROUTE(DITHER0, DSC0,
MMSYS_ROUTE(DITHER, 0, DSC, 0,
MT8188_VDO0_DSC_WARP_SEL, MT8188_SEL_IN_DSC_WRAP0C0_IN_FROM_MASK,
MT8188_SEL_IN_DSC_WRAP0C0_IN_FROM_DISP_DITHER0),
MMSYS_ROUTE(DITHER0, DP_INTF0,
MMSYS_ROUTE(DITHER, 0, DP_INTF, 0,
MT8188_VDO0_DP_INTF0_SEL_IN, MT8188_SEL_IN_DP_INTF0_FROM_MASK,
MT8188_SEL_IN_DP_INTF0_FROM_DISP_DITHER0),
MMSYS_ROUTE(DSC0, MERGE0,
MMSYS_ROUTE(DSC, 0, MERGE, 0,
MT8188_VDO0_VPP_MERGE_SEL, MT8188_SEL_IN_VPP_MERGE_FROM_MASK,
MT8188_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT),
MMSYS_ROUTE(MERGE0, DP_INTF0,
MMSYS_ROUTE(MERGE, 0, DP_INTF, 0,
MT8188_VDO0_DP_INTF0_SEL_IN, MT8188_SEL_IN_DP_INTF0_FROM_MASK,
MT8188_SEL_IN_DP_INTF0_FROM_VPP_MERGE),
MMSYS_ROUTE(DSC0, DSI0,
MMSYS_ROUTE(DSC, 0, DSI, 0,
MT8188_VDO0_DSI0_SEL_IN, MT8188_SEL_IN_DSI0_FROM_MASK,
MT8188_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT),
MMSYS_ROUTE(RDMA0, COLOR0,
MMSYS_ROUTE(RDMA, 0, COLOR, 0,
MT8188_VDO0_DISP_RDMA_SEL, GENMASK(1, 0),
MT8188_SOUT_DISP_RDMA0_TO_DISP_COLOR0),
MMSYS_ROUTE(DITHER0, DSC0,
MMSYS_ROUTE(DITHER, 0, DSC, 0,
MT8188_VDO0_DISP_DITHER0_SEL_OUT, MT8188_SOUT_DISP_DITHER0_TO_MASK,
MT8188_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN),
MMSYS_ROUTE(DITHER0, DSI0,
MMSYS_ROUTE(DITHER, 0, DSI, 0,
MT8188_VDO0_DISP_DITHER0_SEL_OUT, MT8188_SOUT_DISP_DITHER0_TO_MASK,
MT8188_SOUT_DISP_DITHER0_TO_DSI0),
MMSYS_ROUTE(DITHER0, MERGE0,
MMSYS_ROUTE(DITHER, 0, MERGE, 0,
MT8188_VDO0_DISP_DITHER0_SEL_OUT, MT8188_SOUT_DISP_DITHER0_TO_MASK,
MT8188_SOUT_DISP_DITHER0_TO_VPP_MERGE0),
MMSYS_ROUTE(DITHER0, DP_INTF0,
MMSYS_ROUTE(DITHER, 0, DP_INTF, 0,
MT8188_VDO0_DISP_DITHER0_SEL_OUT, MT8188_SOUT_DISP_DITHER0_TO_MASK,
MT8188_SOUT_DISP_DITHER0_TO_DP_INTF0),
MMSYS_ROUTE(MERGE0, DP_INTF0,
MMSYS_ROUTE(MERGE, 0, DP_INTF, 0,
MT8188_VDO0_VPP_MERGE_SEL, MT8188_SOUT_VPP_MERGE_TO_MASK,
MT8188_SOUT_VPP_MERGE_TO_DP_INTF0),
MMSYS_ROUTE(MERGE0, DPI0,
MMSYS_ROUTE(MERGE, 0, DPI, 0,
MT8188_VDO0_VPP_MERGE_SEL, MT8188_SOUT_VPP_MERGE_TO_MASK,
MT8188_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0),
MMSYS_ROUTE(MERGE0, WDMA0,
MMSYS_ROUTE(MERGE, 0, WDMA, 0,
MT8188_VDO0_VPP_MERGE_SEL, MT8188_SOUT_VPP_MERGE_TO_MASK,
MT8188_SOUT_VPP_MERGE_TO_DISP_WDMA0),
MMSYS_ROUTE(MERGE0, DSC0,
MMSYS_ROUTE(MERGE, 0, DSC, 0,
MT8188_VDO0_VPP_MERGE_SEL, MT8188_SOUT_VPP_MERGE_TO_MASK,
MT8188_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN),
MMSYS_ROUTE(DSC0, DSI0,
MMSYS_ROUTE(DSC, 0, DSI, 0,
MT8188_VDO0_DSC_WARP_SEL, MT8188_SOUT_DSC_WRAP0_OUT_TO_MASK,
MT8188_SOUT_DSC_WRAP0_OUT_TO_DSI0),
MMSYS_ROUTE(DSC0, MERGE0,
MMSYS_ROUTE(DSC, 0, MERGE, 0,
MT8188_VDO0_DSC_WARP_SEL, MT8188_SOUT_DSC_WRAP0_OUT_TO_MASK,
MT8188_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE),
};
static const struct mtk_mmsys_routes mmsys_mt8188_vdo1_routing_table[] = {
MMSYS_ROUTE(MDP_RDMA0, MERGE1,
MMSYS_ROUTE(MDP_RDMA, 0, MERGE, 1,
MT8188_VDO1_VPP_MERGE0_P0_SEL_IN, GENMASK(0, 0),
MT8188_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0),
MMSYS_ROUTE(MDP_RDMA1, MERGE1,
MMSYS_ROUTE(MDP_RDMA, 1, MERGE, 1,
MT8188_VDO1_VPP_MERGE0_P1_SEL_IN, GENMASK(0, 0),
MT8188_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1),
MMSYS_ROUTE(MDP_RDMA2, MERGE2,
MMSYS_ROUTE(MDP_RDMA, 2, MERGE, 2,
MT8188_VDO1_VPP_MERGE1_P0_SEL_IN, GENMASK(0, 0),
MT8188_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2),
MMSYS_ROUTE(MERGE1, ETHDR_MIXER,
MMSYS_ROUTE(MERGE, 1, ETHDR_MIXER, 0,
MT8188_VDO1_MERGE0_ASYNC_SOUT_SEL, GENMASK(1, 0),
MT8188_SOUT_TO_MIXER_IN1_SEL),
MMSYS_ROUTE(MERGE2, ETHDR_MIXER,
MMSYS_ROUTE(MERGE, 2, ETHDR_MIXER, 0,
MT8188_VDO1_MERGE1_ASYNC_SOUT_SEL, GENMASK(1, 0),
MT8188_SOUT_TO_MIXER_IN2_SEL),
MMSYS_ROUTE(MERGE3, ETHDR_MIXER,
MMSYS_ROUTE(MERGE, 3, ETHDR_MIXER, 0,
MT8188_VDO1_MERGE2_ASYNC_SOUT_SEL, GENMASK(1, 0),
MT8188_SOUT_TO_MIXER_IN3_SEL),
MMSYS_ROUTE(MERGE4, ETHDR_MIXER,
MMSYS_ROUTE(MERGE, 4, ETHDR_MIXER, 0,
MT8188_VDO1_MERGE3_ASYNC_SOUT_SEL, GENMASK(1, 0),
MT8188_SOUT_TO_MIXER_IN4_SEL),
MMSYS_ROUTE(ETHDR_MIXER, MERGE5,
MMSYS_ROUTE(ETHDR_MIXER, 0, MERGE, 5,
MT8188_VDO1_MIXER_OUT_SOUT_SEL, GENMASK(0, 0),
MT8188_MIXER_SOUT_TO_MERGE4_ASYNC_SEL),
MMSYS_ROUTE(MERGE1, ETHDR_MIXER,
MMSYS_ROUTE(MERGE, 1, ETHDR_MIXER, 0,
MT8188_VDO1_MIXER_IN1_SEL_IN, GENMASK(0, 0),
MT8188_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT),
MMSYS_ROUTE(MERGE2, ETHDR_MIXER,
MMSYS_ROUTE(MERGE, 2, ETHDR_MIXER, 0,
MT8188_VDO1_MIXER_IN2_SEL_IN, GENMASK(0, 0),
MT8188_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT),
MMSYS_ROUTE(MERGE3, ETHDR_MIXER,
MMSYS_ROUTE(MERGE, 3, ETHDR_MIXER, 0,
MT8188_VDO1_MIXER_IN3_SEL_IN, GENMASK(0, 0),
MT8188_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT),
MMSYS_ROUTE(MERGE4, ETHDR_MIXER,
MMSYS_ROUTE(MERGE, 4, ETHDR_MIXER, 0,
MT8188_VDO1_MIXER_IN4_SEL_IN, GENMASK(0, 0),
MT8188_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT),
MMSYS_ROUTE(ETHDR_MIXER, MERGE5,
MMSYS_ROUTE(ETHDR_MIXER, 0, MERGE, 5,
MT8188_VDO1_MIXER_SOUT_SEL_IN, GENMASK(2, 0),
MT8188_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER),
MMSYS_ROUTE(ETHDR_MIXER, MERGE5,
MMSYS_ROUTE(ETHDR_MIXER, 0, MERGE, 5,
MT8188_VDO1_MERGE4_ASYNC_SEL_IN, GENMASK(2, 0),
MT8188_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT),
MMSYS_ROUTE(MERGE5, DPI1,
MMSYS_ROUTE(MERGE, 5, DPI, 1,
MT8188_VDO1_DISP_DPI1_SEL_IN, GENMASK(1, 0),
MT8188_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT),
MMSYS_ROUTE(MERGE5, DPI1,
MMSYS_ROUTE(MERGE, 5, DPI, 1,
MT8188_VDO1_MERGE4_SOUT_SEL, GENMASK(3, 0),
MT8188_MERGE4_SOUT_TO_DPI1_SEL),
MMSYS_ROUTE(MERGE5, DP_INTF1,
MMSYS_ROUTE(MERGE, 5, DP_INTF, 1,
MT8188_VDO1_DISP_DP_INTF0_SEL_IN, GENMASK(1, 0),
MT8188_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT),
MMSYS_ROUTE(MERGE5, DP_INTF1,
MMSYS_ROUTE(MERGE, 5, DP_INTF, 1,
MT8188_VDO1_MERGE4_SOUT_SEL, GENMASK(3, 0),
MT8188_MERGE4_SOUT_TO_DP_INTF0_SEL),
};

20
drivers/soc/mediatek/mt8192-mmsys.h
View File

@@ -31,34 +31,34 @@
#define MT8192_DSI0_SEL_IN_DITHER0 0x1
static const struct mtk_mmsys_routes mmsys_mt8192_routing_table[] = {
MMSYS_ROUTE(OVL_2L0, RDMA0,
MMSYS_ROUTE(OVL_2L, 0, RDMA, 0,
MT8192_DISP_OVL0_2L_MOUT_EN, MT8192_OVL0_MOUT_EN_DISP_RDMA0,
MT8192_OVL0_MOUT_EN_DISP_RDMA0),
MMSYS_ROUTE(OVL_2L2, RDMA4,
MMSYS_ROUTE(OVL_2L, 2, RDMA, 4,
MT8192_DISP_OVL2_2L_MOUT_EN, MT8192_OVL2_2L_MOUT_EN_RDMA4,
MT8192_OVL2_2L_MOUT_EN_RDMA4),
MMSYS_ROUTE(DITHER0, DSI0,
MMSYS_ROUTE(DITHER, 0, DSI, 0,
MT8192_DISP_DITHER0_MOUT_EN, MT8192_DITHER0_MOUT_IN_DSI0,
MT8192_DITHER0_MOUT_IN_DSI0),
MMSYS_ROUTE(OVL_2L0, RDMA0,
MMSYS_ROUTE(OVL_2L, 0, RDMA, 0,
MT8192_DISP_RDMA0_SEL_IN, MT8192_RDMA0_SEL_IN_OVL0_2L,
MT8192_RDMA0_SEL_IN_OVL0_2L),
MMSYS_ROUTE(CCORR, AAL0,
MMSYS_ROUTE(CCORR, 0, AAL, 0,
MT8192_DISP_AAL0_SEL_IN, MT8192_AAL0_SEL_IN_CCORR0,
MT8192_AAL0_SEL_IN_CCORR0),
MMSYS_ROUTE(DITHER0, DSI0,
MMSYS_ROUTE(DITHER, 0, DSI, 0,
MT8192_DISP_DSI0_SEL_IN, MT8192_DSI0_SEL_IN_DITHER0,
MT8192_DSI0_SEL_IN_DITHER0),
MMSYS_ROUTE(RDMA0, COLOR0,
MMSYS_ROUTE(RDMA, 0, COLOR, 0,
MT8192_DISP_RDMA0_SOUT_SEL, MT8192_RDMA0_SOUT_COLOR0,
MT8192_RDMA0_SOUT_COLOR0),
MMSYS_ROUTE(CCORR, AAL0,
MMSYS_ROUTE(CCORR, 0, AAL, 0,
MT8192_DISP_CCORR0_SOUT_SEL, MT8192_CCORR0_SOUT_AAL0,
MT8192_CCORR0_SOUT_AAL0),
MMSYS_ROUTE(OVL0, OVL_2L0,
MMSYS_ROUTE(OVL, 0, OVL_2L, 0,
MT8192_MMSYS_OVL_MOUT_EN, MT8192_DISP_OVL0_GO_BG,
MT8192_DISP_OVL0_GO_BG),
MMSYS_ROUTE(OVL_2L0, RDMA0,
MMSYS_ROUTE(OVL_2L, 0, RDMA, 0,
MT8192_MMSYS_OVL_MOUT_EN, MT8192_DISP_OVL0_2L_GO_BLEND,
MT8192_DISP_OVL0_2L_GO_BLEND),
};

181
drivers/soc/mediatek/mt8195-mmsys.h
View File

@@ -160,278 +160,279 @@
#define MT8195_SVPP3_MDP_RSZ BIT(5)
static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
MMSYS_ROUTE(OVL0, RDMA0,
MMSYS_ROUTE(OVL, 0, RDMA, 0,
MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0,
MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0),
MMSYS_ROUTE(OVL0, WDMA0,
MMSYS_ROUTE(OVL, 0, WDMA, 0,
MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0,
MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0),
MMSYS_ROUTE(OVL0, OVL1,
MMSYS_ROUTE(OVL, 0, OVL, 1,
MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1,
MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1),
MMSYS_ROUTE(OVL1, RDMA1,
MMSYS_ROUTE(OVL, 1, RDMA, 1,
MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1,
MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1),
MMSYS_ROUTE(OVL1, WDMA1,
MMSYS_ROUTE(OVL, 1, WDMA, 1,
MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1,
MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1),
MMSYS_ROUTE(OVL1, OVL0,
MMSYS_ROUTE(OVL, 1, OVL, 0,
MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0,
MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0),
MMSYS_ROUTE(DSC0, MERGE0,
MMSYS_ROUTE(DSC, 0, MERGE, 0,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT),
MMSYS_ROUTE(DITHER1, MERGE0,
MMSYS_ROUTE(DITHER, 1, MERGE, 0,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1),
MMSYS_ROUTE(MERGE5, MERGE0,
MMSYS_ROUTE(MERGE, 5, MERGE, 0,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0),
MMSYS_ROUTE(DITHER0, DSC0,
MMSYS_ROUTE(DITHER, 0, DSC, 0,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0),
MMSYS_ROUTE(MERGE0, DSC0,
MMSYS_ROUTE(MERGE, 0, DSC, 0,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE),
MMSYS_ROUTE(DITHER1, DSC1,
MMSYS_ROUTE(DITHER, 1, DSC, 1,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK,
MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1),
MMSYS_ROUTE(MERGE0, DSC1,
MMSYS_ROUTE(MERGE, 0, DSC, 1,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK,
MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE),
MMSYS_ROUTE(MERGE0, DP_INTF1,
MMSYS_ROUTE(MERGE, 0, DP_INTF, 1,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE),
MMSYS_ROUTE(MERGE0, DPI0,
MMSYS_ROUTE(MERGE, 0, DPI, 0,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE),
MMSYS_ROUTE(MERGE0, DPI1,
MMSYS_ROUTE(MERGE, 0, DPI, 1,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE),
MMSYS_ROUTE(DSC1, DP_INTF1,
MMSYS_ROUTE(DSC, 1, DP_INTF, 1,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT),
MMSYS_ROUTE(DSC1, DPI0,
MMSYS_ROUTE(DSC, 1, DPI, 0,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT),
MMSYS_ROUTE(DSC1, DPI1,
MMSYS_ROUTE(DSC, 1, DPI, 1,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT),
MMSYS_ROUTE(DSC0, DP_INTF1,
MMSYS_ROUTE(DSC, 0, DP_INTF, 1,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT),
MMSYS_ROUTE(DSC0, DPI0,
MMSYS_ROUTE(DSC, 0, DPI, 0,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT),
MMSYS_ROUTE(DSC0, DPI1,
MMSYS_ROUTE(DSC, 0, DPI, 1,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT),
MMSYS_ROUTE(DSC1, DP_INTF0,
MMSYS_ROUTE(DSC, 1, DP_INTF, 0,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT),
MMSYS_ROUTE(MERGE0, DP_INTF0,
MMSYS_ROUTE(MERGE, 0, DP_INTF, 0,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE),
MMSYS_ROUTE(MERGE5, DP_INTF0,
MMSYS_ROUTE(MERGE, 5, DP_INTF, 0,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0),
MMSYS_ROUTE(DSC0, DSI0,
MMSYS_ROUTE(DSC, 0, DSI, 0,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT),
MMSYS_ROUTE(DITHER0, DSI0,
MMSYS_ROUTE(DITHER, 0, DSI, 0,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0),
MMSYS_ROUTE(DSC1, DSI1,
MMSYS_ROUTE(DSC, 1, DSI, 1,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK,
MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT),
MMSYS_ROUTE(MERGE0, DSI1,
MMSYS_ROUTE(MERGE, 0, DSI, 1,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK,
MT8195_SEL_IN_DSI1_FROM_VPP_MERGE),
MMSYS_ROUTE(OVL1, WDMA1,
MMSYS_ROUTE(OVL, 1, WDMA, 1,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK,
MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1),
MMSYS_ROUTE(MERGE0, WDMA1,
MMSYS_ROUTE(MERGE, 0, WDMA, 1,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK,
MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE),
MMSYS_ROUTE(DSC1, DSI1,
MMSYS_ROUTE(DSC, 1, DSI, 1,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN),
MMSYS_ROUTE(DSC1, DP_INTF0,
MMSYS_ROUTE(DSC, 1, DP_INTF, 0,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN),
MMSYS_ROUTE(DSC1, DP_INTF1,
MMSYS_ROUTE(DSC, 1, DP_INTF, 1,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN),
MMSYS_ROUTE(DSC1, DPI0,
MMSYS_ROUTE(DSC, 1, DPI, 0,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN),
MMSYS_ROUTE(DSC1, DPI1,
MMSYS_ROUTE(DSC, 1, DPI, 1,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN),
MMSYS_ROUTE(DSC1, MERGE0,
MMSYS_ROUTE(DSC, 1, MERGE, 0,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN),
MMSYS_ROUTE(DITHER1, DSI1,
MMSYS_ROUTE(DITHER, 1, DSI, 1,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1),
MMSYS_ROUTE(DITHER1, DP_INTF0,
MMSYS_ROUTE(DITHER, 1, DP_INTF, 0,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1),
MMSYS_ROUTE(DITHER1, DPI0,
MMSYS_ROUTE(DITHER, 1, DPI, 0,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1),
MMSYS_ROUTE(DITHER1, DPI1,
MMSYS_ROUTE(DITHER, 1, DPI, 1,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1),
MMSYS_ROUTE(OVL0, WDMA0,
MMSYS_ROUTE(OVL, 0, WDMA, 0,
MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA0_FROM_MASK,
MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0),
MMSYS_ROUTE(DITHER0, DSC0,
MMSYS_ROUTE(DITHER, 0, DSC, 0,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN),
MMSYS_ROUTE(DITHER0, DSI0,
MMSYS_ROUTE(DITHER, 0, DSI, 0,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
MT8195_SOUT_DISP_DITHER0_TO_DSI0),
MMSYS_ROUTE(DITHER1, DSC1,
MMSYS_ROUTE(DITHER, 1, DSC, 1,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN),
MMSYS_ROUTE(DITHER1, MERGE0,
MMSYS_ROUTE(DITHER, 1, MERGE, 0,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE),
MMSYS_ROUTE(DITHER1, DSI1,
MMSYS_ROUTE(DITHER, 1, DSI, 1,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT),
MMSYS_ROUTE(DITHER1, DP_INTF0,
MMSYS_ROUTE(DITHER, 1, DP_INTF, 0,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT),
MMSYS_ROUTE(DITHER1, DP_INTF1,
MMSYS_ROUTE(DITHER, 1, DP_INTF, 1,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT),
MMSYS_ROUTE(DITHER1, DPI0,
MMSYS_ROUTE(DITHER, 1, DPI, 0,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT),
MMSYS_ROUTE(DITHER1, DPI1,
MMSYS_ROUTE(DITHER, 1, DPI, 1,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT),
MMSYS_ROUTE(MERGE5, MERGE0,
MMSYS_ROUTE(MERGE, 5, MERGE, 0,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK,
MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE),
MMSYS_ROUTE(MERGE5, DP_INTF0,
MMSYS_ROUTE(MERGE, 5, DP_INTF, 0,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK,
MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0),
MMSYS_ROUTE(MERGE0, DSI1,
MMSYS_ROUTE(MERGE, 0, DSI, 1,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
MT8195_SOUT_VPP_MERGE_TO_DSI1),
MMSYS_ROUTE(MERGE0, DP_INTF0,
MMSYS_ROUTE(MERGE, 0, DP_INTF, 0,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
MT8195_SOUT_VPP_MERGE_TO_DP_INTF0),
MMSYS_ROUTE(MERGE0, DP_INTF1,
MMSYS_ROUTE(MERGE, 0, DP_INTF, 1,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0),
MMSYS_ROUTE(MERGE0, DPI0,
MMSYS_ROUTE(MERGE, 0, DPI, 0,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0),
MMSYS_ROUTE(MERGE0, DPI1,
MMSYS_ROUTE(MERGE, 0, DPI, 1,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0),
MMSYS_ROUTE(MERGE0, WDMA1,
MMSYS_ROUTE(MERGE, 0, WDMA, 1,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1),
MMSYS_ROUTE(MERGE0, DSC0,
MMSYS_ROUTE(MERGE, 0, DSC, 0,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN),
MMSYS_ROUTE(MERGE0, DSC1,
MMSYS_ROUTE(MERGE, 0, DSC, 1,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK,
MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN),
MMSYS_ROUTE(DSC0, DSI0,
MMSYS_ROUTE(DSC, 0, DSI, 0,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0),
MMSYS_ROUTE(DSC0, DP_INTF1,
MMSYS_ROUTE(DSC, 0, DP_INTF, 1,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0),
MMSYS_ROUTE(DSC0, DPI0,
MMSYS_ROUTE(DSC, 0, DPI, 0,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0),
MMSYS_ROUTE(DSC0, DPI1,
MMSYS_ROUTE(DSC, 0, DPI, 1,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0),
MMSYS_ROUTE(DSC0, MERGE0,
MMSYS_ROUTE(DSC, 0, MERGE, 0,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE),
MMSYS_ROUTE(DSC1, DSI1,
MMSYS_ROUTE(DSC, 1, DSI, 1,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1),
MMSYS_ROUTE(DSC1, DP_INTF0,
MMSYS_ROUTE(DSC, 1, DP_INTF, 0,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0),
MMSYS_ROUTE(DSC1, DP_INTF1,
MMSYS_ROUTE(DSC, 1, DP_INTF, 1,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0),
MMSYS_ROUTE(DSC1, DPI0,
MMSYS_ROUTE(DSC, 1, DPI, 0,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0),
MMSYS_ROUTE(DSC1, DPI1,
MMSYS_ROUTE(DSC, 1, DPI, 1,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0),
MMSYS_ROUTE(DSC1, MERGE0,
MMSYS_ROUTE(DSC, 1, MERGE, 0,
MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE),
};
static const struct mtk_mmsys_routes mmsys_mt8195_vdo1_routing_table[] = {
MMSYS_ROUTE(MDP_RDMA0, MERGE1,
MMSYS_ROUTE(MDP_RDMA, 0, MERGE, 1,
MT8195_VDO1_VPP_MERGE0_P0_SEL_IN, GENMASK(0, 0),
MT8195_VPP_MERGE0_P0_SEL_IN_FROM_MDP_RDMA0),
MMSYS_ROUTE(MDP_RDMA1, MERGE1,
MMSYS_ROUTE(MDP_RDMA, 1, MERGE, 1,
MT8195_VDO1_VPP_MERGE0_P1_SEL_IN, GENMASK(0, 0),
MT8195_VPP_MERGE0_P1_SEL_IN_FROM_MDP_RDMA1),
MMSYS_ROUTE(MDP_RDMA2, MERGE2,
MMSYS_ROUTE(MDP_RDMA, 2, MERGE, 2,
MT8195_VDO1_VPP_MERGE1_P0_SEL_IN, GENMASK(0, 0),
MT8195_VPP_MERGE1_P0_SEL_IN_FROM_MDP_RDMA2),
MMSYS_ROUTE(MERGE1, ETHDR_MIXER,
MMSYS_ROUTE(MERGE, 1, ETHDR_MIXER, 0,
MT8195_VDO1_MERGE0_ASYNC_SOUT_SEL, GENMASK(1, 0),
MT8195_SOUT_TO_MIXER_IN1_SEL),
MMSYS_ROUTE(MERGE2, ETHDR_MIXER,
MMSYS_ROUTE(MERGE, 2, ETHDR_MIXER, 0,
MT8195_VDO1_MERGE1_ASYNC_SOUT_SEL, GENMASK(1, 0),
MT8195_SOUT_TO_MIXER_IN2_SEL),
MMSYS_ROUTE(MERGE3, ETHDR_MIXER,
MMSYS_ROUTE(MERGE, 3, ETHDR_MIXER, 0,
MT8195_VDO1_MERGE2_ASYNC_SOUT_SEL, GENMASK(1, 0),
MT8195_SOUT_TO_MIXER_IN3_SEL),
MMSYS_ROUTE(MERGE4, ETHDR_MIXER,
MMSYS_ROUTE(MERGE, 4, ETHDR_MIXER, 0,
MT8195_VDO1_MERGE3_ASYNC_SOUT_SEL, GENMASK(1, 0),
MT8195_SOUT_TO_MIXER_IN4_SEL),
MMSYS_ROUTE(ETHDR_MIXER, MERGE5,
MMSYS_ROUTE(ETHDR_MIXER, 0, MERGE, 5,
MT8195_VDO1_MIXER_OUT_SOUT_SEL, GENMASK(0, 0),
MT8195_MIXER_SOUT_TO_MERGE4_ASYNC_SEL),
MMSYS_ROUTE(MERGE1, ETHDR_MIXER,
MMSYS_ROUTE(MERGE, 1, ETHDR_MIXER, 0,
MT8195_VDO1_MIXER_IN1_SEL_IN, GENMASK(0, 0),
MT8195_MIXER_IN1_SEL_IN_FROM_MERGE0_ASYNC_SOUT),
MMSYS_ROUTE(MERGE2, ETHDR_MIXER,
MMSYS_ROUTE(MERGE, 2, ETHDR_MIXER, 0,
MT8195_VDO1_MIXER_IN2_SEL_IN, GENMASK(0, 0),
MT8195_MIXER_IN2_SEL_IN_FROM_MERGE1_ASYNC_SOUT),
MMSYS_ROUTE(MERGE3, ETHDR_MIXER,
MMSYS_ROUTE(MERGE, 3, ETHDR_MIXER, 0,
MT8195_VDO1_MIXER_IN3_SEL_IN, GENMASK(0, 0),
MT8195_MIXER_IN3_SEL_IN_FROM_MERGE2_ASYNC_SOUT),
MMSYS_ROUTE(MERGE4, ETHDR_MIXER,
MMSYS_ROUTE(MERGE, 4, ETHDR_MIXER, 0,
MT8195_VDO1_MIXER_IN4_SEL_IN, GENMASK(0, 0),
MT8195_MIXER_IN4_SEL_IN_FROM_MERGE3_ASYNC_SOUT),
MMSYS_ROUTE(ETHDR_MIXER, MERGE5,
MMSYS_ROUTE(ETHDR_MIXER, 0, MERGE, 5,
MT8195_VDO1_MIXER_SOUT_SEL_IN, GENMASK(2, 0),
MT8195_MIXER_SOUT_SEL_IN_FROM_DISP_MIXER),
MMSYS_ROUTE(ETHDR_MIXER, MERGE5,
MMSYS_ROUTE(ETHDR_MIXER, 0, MERGE, 5,
MT8195_VDO1_MERGE4_ASYNC_SEL_IN, GENMASK(2, 0),
MT8195_MERGE4_ASYNC_SEL_IN_FROM_MIXER_OUT_SOUT),
MMSYS_ROUTE(MERGE5, DPI1,
MMSYS_ROUTE(MERGE, 5, DPI, 1,
MT8195_VDO1_DISP_DPI1_SEL_IN, GENMASK(1, 0),
MT8195_DISP_DPI1_SEL_IN_FROM_VPP_MERGE4_MOUT),
MMSYS_ROUTE(MERGE5, DPI1,
MMSYS_ROUTE(MERGE, 5, DPI, 1,
MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0),
MT8195_MERGE4_SOUT_TO_DPI1_SEL),
MMSYS_ROUTE(MERGE5, DP_INTF1,
MMSYS_ROUTE(MERGE, 5, DP_INTF, 1,
MT8195_VDO1_DISP_DP_INTF0_SEL_IN, GENMASK(1, 0),
MT8195_DISP_DP_INTF0_SEL_IN_FROM_VPP_MERGE4_MOUT),
MMSYS_ROUTE(MERGE5, DP_INTF1,
MMSYS_ROUTE(MERGE, 5, DP_INTF, 1,
MT8195_VDO1_MERGE4_SOUT_SEL, GENMASK(1, 0),
MT8195_MERGE4_SOUT_TO_DP_INTF0_SEL),
};
#endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */

20
drivers/soc/mediatek/mt8365-mmsys.h
View File

@@ -28,35 +28,35 @@
#define MT8365_DPI0_SEL_IN_RDMA1 0x0
static const struct mtk_mmsys_routes mt8365_mmsys_routing_table[] = {
MMSYS_ROUTE(OVL0, RDMA0,
MMSYS_ROUTE(OVL, 0, RDMA, 0,
MT8365_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN,
MT8365_DISP_MS_IN_OUT_MASK, MT8365_OVL0_MOUT_PATH0_SEL),
MMSYS_ROUTE(OVL0, RDMA0,
MMSYS_ROUTE(OVL, 0, RDMA, 0,
MT8365_DISP_REG_CONFIG_DISP_RDMA0_SEL_IN,
MT8365_DISP_MS_IN_OUT_MASK, MT8365_RDMA0_SEL_IN_OVL0),
MMSYS_ROUTE(RDMA0, COLOR0,
MMSYS_ROUTE(RDMA, 0, COLOR, 0,
MT8365_DISP_REG_CONFIG_DISP_RDMA0_SOUT_SEL,
MT8365_DISP_MS_IN_OUT_MASK, MT8365_RDMA0_SOUT_COLOR0),
MMSYS_ROUTE(COLOR0, CCORR,
MMSYS_ROUTE(COLOR, 0, CCORR, 0,
MT8365_DISP_REG_CONFIG_DISP_COLOR0_SEL_IN,
MT8365_DISP_MS_IN_OUT_MASK, MT8365_DISP_COLOR_SEL_IN_COLOR0),
MMSYS_ROUTE(DITHER0, DSI0,
MMSYS_ROUTE(DITHER, 0, DSI, 0,
MT8365_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN,
MT8365_DISP_MS_IN_OUT_MASK, MT8365_DITHER_MOUT_EN_DSI0),
MMSYS_ROUTE(DITHER0, DSI0,
MMSYS_ROUTE(DITHER, 0, DSI, 0,
MT8365_DISP_REG_CONFIG_DISP_DSI0_SEL_IN,
MT8365_DISP_MS_IN_OUT_MASK, MT8365_DSI0_SEL_IN_DITHER),
MMSYS_ROUTE(RDMA0, COLOR0,
MMSYS_ROUTE(RDMA, 0, COLOR, 0,
MT8365_DISP_REG_CONFIG_DISP_RDMA0_RSZ0_SEL_IN,
MT8365_DISP_MS_IN_OUT_MASK, MT8365_RDMA0_RSZ0_SEL_IN_RDMA0),
MMSYS_ROUTE(RDMA1, DPI0,
MMSYS_ROUTE(RDMA, 1, DPI, 0,
MT8365_DISP_REG_CONFIG_DISP_LVDS_SYS_CFG_00,
MT8365_LVDS_SYS_CFG_00_SEL_LVDS_PXL_CLK,
MT8365_LVDS_SYS_CFG_00_SEL_LVDS_PXL_CLK),
MMSYS_ROUTE(RDMA1, DPI0,
MMSYS_ROUTE(RDMA, 1, DPI, 0,
MT8365_DISP_REG_CONFIG_DISP_DPI0_SEL_IN,
MT8365_DISP_MS_IN_OUT_MASK, MT8365_DPI0_SEL_IN_RDMA1),
MMSYS_ROUTE(RDMA1, DPI0,
MMSYS_ROUTE(RDMA, 1, DPI, 0,
MT8365_DISP_REG_CONFIG_DISP_RDMA1_SOUT_SEL,
MT8365_DISP_MS_IN_OUT_MASK, MT8365_RDMA1_SOUT_DPI0),
};

1
drivers/soc/mediatek/mtk-dvfsrc.c
View File

@@ -862,6 +862,7 @@ static const struct of_device_id mtk_dvfsrc_of_match[] = {
{ .compatible = "mediatek,mt8196-dvfsrc", .data = &mt8196_data },
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, mtk_dvfsrc_of_match);
static struct platform_driver mtk_dvfsrc_driver = {
.probe = mtk_dvfsrc_probe,

300
drivers/soc/mediatek/mtk-mmsys.h
View File

@@ -80,18 +80,25 @@
#define MMSYS_RST_NR(bank, bit) (((bank) * 32) + (bit))
/* Temporary compatibility definitions */
#define DDP_COMPONENT_BLS0 DDP_COMPONENT_BLS
#define DDP_COMPONENT_CCORR0 DDP_COMPONENT_CCORR
#define DDP_COMPONENT_UFOE0 DDP_COMPONENT_UFOE
#define DDP_COMPONENT_GAMMA0 DDP_COMPONENT_GAMMA
#define DDP_COMPONENT_ETHDR_MIXER0 DDP_COMPONENT_ETHDR_MIXER
/*
* This macro adds a compile time check to make sure that the in/out
* selection bit(s) fit in the register mask, similar to bitfield
* macros, but this does not transform the value.
*/
#define MMSYS_ROUTE(from, to, reg_addr, reg_mask, selection) \
{ DDP_COMPONENT_##from, DDP_COMPONENT_##to, reg_addr, reg_mask, \
(__BUILD_BUG_ON_ZERO_MSG((reg_mask) == 0, "Invalid mask") + \
__BUILD_BUG_ON_ZERO_MSG(~(reg_mask) & (selection), \
#selection " does not fit in " \
#reg_mask) + \
(selection)) \
#define MMSYS_ROUTE(from, fsid, to, tsid, reg_addr, reg_mask, selection) \
{ DDP_COMPONENT_##from##fsid, DDP_COMPONENT_##to##tsid, reg_addr, reg_mask, \
(__BUILD_BUG_ON_ZERO_MSG((reg_mask) == 0, "Invalid mask") + \
__BUILD_BUG_ON_ZERO_MSG(~(reg_mask) & (selection), \
#selection " does not fit in " \
#reg_mask) + \
(selection)) \
}
struct mtk_mmsys_routes {
@@ -151,171 +158,120 @@ struct mtk_mmsys_driver_data {
* to an independent table.
*/
static const struct mtk_mmsys_routes mmsys_default_routing_table[] = {
{
DDP_COMPONENT_BLS, DDP_COMPONENT_DSI0,
DISP_REG_CONFIG_OUT_SEL, BLS_RDMA1_DSI_DPI_MASK,
BLS_TO_DSI_RDMA1_TO_DPI1
}, {
DDP_COMPONENT_BLS, DDP_COMPONENT_DSI0,
DISP_REG_CONFIG_DSI_SEL, DSI_SEL_IN_MASK,
DSI_SEL_IN_BLS
}, {
DDP_COMPONENT_BLS, DDP_COMPONENT_DPI0,
DISP_REG_CONFIG_OUT_SEL, BLS_RDMA1_DSI_DPI_MASK,
BLS_TO_DPI_RDMA1_TO_DSI
}, {
DDP_COMPONENT_BLS, DDP_COMPONENT_DPI0,
DISP_REG_CONFIG_DSI_SEL, DSI_SEL_IN_MASK,
DSI_SEL_IN_RDMA
}, {
DDP_COMPONENT_BLS, DDP_COMPONENT_DPI0,
DISP_REG_CONFIG_DPI_SEL, DPI_SEL_IN_MASK,
DPI_SEL_IN_BLS
}, {
DDP_COMPONENT_GAMMA, DDP_COMPONENT_RDMA1,
DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN, GAMMA_MOUT_EN_RDMA1,
GAMMA_MOUT_EN_RDMA1
}, {
DDP_COMPONENT_OD0, DDP_COMPONENT_RDMA0,
DISP_REG_CONFIG_DISP_OD_MOUT_EN, OD_MOUT_EN_RDMA0,
OD_MOUT_EN_RDMA0
}, {
DDP_COMPONENT_OD1, DDP_COMPONENT_RDMA1,
DISP_REG_CONFIG_DISP_OD_MOUT_EN, OD1_MOUT_EN_RDMA1,
OD1_MOUT_EN_RDMA1
}, {
DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_COLOR0,
OVL0_MOUT_EN_COLOR0
}, {
DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, COLOR0_SEL_IN_OVL0,
COLOR0_SEL_IN_OVL0
}, {
DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
DISP_REG_CONFIG_DISP_OVL_MOUT_EN, OVL_MOUT_EN_RDMA,
OVL_MOUT_EN_RDMA
}, {
DDP_COMPONENT_OVL1, DDP_COMPONENT_COLOR1,
DISP_REG_CONFIG_DISP_OVL1_MOUT_EN, OVL1_MOUT_EN_COLOR1,
OVL1_MOUT_EN_COLOR1
}, {
DDP_COMPONENT_OVL1, DDP_COMPONENT_COLOR1,
DISP_REG_CONFIG_DISP_COLOR1_SEL_IN, COLOR1_SEL_IN_OVL1,
COLOR1_SEL_IN_OVL1
}, {
DDP_COMPONENT_RDMA0, DDP_COMPONENT_DPI0,
DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
RDMA0_SOUT_DPI0
}, {
DDP_COMPONENT_RDMA0, DDP_COMPONENT_DPI1,
DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
RDMA0_SOUT_DPI1
}, {
DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI1,
DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
RDMA0_SOUT_DSI1
}, {
DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI2,
DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
RDMA0_SOUT_DSI2
}, {
DDP_COMPONENT_RDMA0, DDP_COMPONENT_DSI3,
DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
RDMA0_SOUT_DSI3
}, {
DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
RDMA1_SOUT_DPI0
}, {
DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI0,
DISP_REG_CONFIG_DPI_SEL_IN, DPI0_SEL_IN_MASK,
DPI0_SEL_IN_RDMA1
}, {
DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI1,
DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
RDMA1_SOUT_DPI1
}, {
DDP_COMPONENT_RDMA1, DDP_COMPONENT_DPI1,
DISP_REG_CONFIG_DPI_SEL_IN, DPI1_SEL_IN_MASK,
DPI1_SEL_IN_RDMA1
}, {
DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI0,
DISP_REG_CONFIG_DSIE_SEL_IN, DSI0_SEL_IN_MASK,
DSI0_SEL_IN_RDMA1
}, {
DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI1,
DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
RDMA1_SOUT_DSI1
}, {
DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI1,
DISP_REG_CONFIG_DSIO_SEL_IN, DSI1_SEL_IN_MASK,
DSI1_SEL_IN_RDMA1
}, {
DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI2,
DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
RDMA1_SOUT_DSI2
}, {
DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI2,
DISP_REG_CONFIG_DSIE_SEL_IN, DSI2_SEL_IN_MASK,
DSI2_SEL_IN_RDMA1
}, {
DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI3,
DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
RDMA1_SOUT_DSI3
}, {
DDP_COMPONENT_RDMA1, DDP_COMPONENT_DSI3,
DISP_REG_CONFIG_DSIO_SEL_IN, DSI3_SEL_IN_MASK,
DSI3_SEL_IN_RDMA1
}, {
DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI0,
DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
RDMA2_SOUT_DPI0
}, {
DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI0,
DISP_REG_CONFIG_DPI_SEL_IN, DPI0_SEL_IN_MASK,
DPI0_SEL_IN_RDMA2
}, {
DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI1,
DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
RDMA2_SOUT_DPI1
}, {
DDP_COMPONENT_RDMA2, DDP_COMPONENT_DPI1,
DISP_REG_CONFIG_DPI_SEL_IN, DPI1_SEL_IN_MASK,
DPI1_SEL_IN_RDMA2
}, {
DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI0,
DISP_REG_CONFIG_DSIE_SEL_IN, DSI0_SEL_IN_MASK,
DSI0_SEL_IN_RDMA2
}, {
DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI1,
DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
RDMA2_SOUT_DSI1
}, {
DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI1,
DISP_REG_CONFIG_DSIO_SEL_IN, DSI1_SEL_IN_MASK,
DSI1_SEL_IN_RDMA2
}, {
DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI2,
DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
RDMA2_SOUT_DSI2
}, {
DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI2,
DISP_REG_CONFIG_DSIE_SEL_IN, DSI2_SEL_IN_MASK,
DSI2_SEL_IN_RDMA2
}, {
DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI3,
DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
RDMA2_SOUT_DSI3
}, {
DDP_COMPONENT_RDMA2, DDP_COMPONENT_DSI3,
DISP_REG_CONFIG_DSIO_SEL_IN, DSI3_SEL_IN_MASK,
DSI3_SEL_IN_RDMA2
}, {
DDP_COMPONENT_UFOE, DDP_COMPONENT_DSI0,
DISP_REG_CONFIG_DISP_UFOE_MOUT_EN, UFOE_MOUT_EN_DSI0,
UFOE_MOUT_EN_DSI0
}
MMSYS_ROUTE(BLS, 0, DSI, 0,
DISP_REG_CONFIG_OUT_SEL, BLS_RDMA1_DSI_DPI_MASK,
BLS_TO_DSI_RDMA1_TO_DPI1),
MMSYS_ROUTE(BLS, 0, DSI, 0,
DISP_REG_CONFIG_DSI_SEL, DSI_SEL_IN_MASK,
DSI_SEL_IN_BLS),
MMSYS_ROUTE(BLS, 0, DPI, 0,
DISP_REG_CONFIG_OUT_SEL, BLS_RDMA1_DSI_DPI_MASK,
BLS_TO_DPI_RDMA1_TO_DSI),
MMSYS_ROUTE(BLS, 0, DPI, 0,
DISP_REG_CONFIG_DSI_SEL, DSI_SEL_IN_MASK,
DSI_SEL_IN_RDMA),
MMSYS_ROUTE(BLS, 0, DPI, 0,
DISP_REG_CONFIG_DPI_SEL, DPI_SEL_IN_MASK,
DPI_SEL_IN_BLS),
MMSYS_ROUTE(GAMMA, 0, RDMA, 1,
DISP_REG_CONFIG_DISP_GAMMA_MOUT_EN, GAMMA_MOUT_EN_RDMA1,
GAMMA_MOUT_EN_RDMA1),
MMSYS_ROUTE(OD, 0, RDMA, 0,
DISP_REG_CONFIG_DISP_OD_MOUT_EN, OD_MOUT_EN_RDMA0,
OD_MOUT_EN_RDMA0),
MMSYS_ROUTE(OD, 1, RDMA, 1,
DISP_REG_CONFIG_DISP_OD_MOUT_EN, OD1_MOUT_EN_RDMA1,
OD1_MOUT_EN_RDMA1),
MMSYS_ROUTE(OVL, 0, COLOR, 0,
DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_COLOR0,
OVL0_MOUT_EN_COLOR0),
MMSYS_ROUTE(OVL, 0, COLOR, 0,
DISP_REG_CONFIG_DISP_COLOR0_SEL_IN, COLOR0_SEL_IN_OVL0,
COLOR0_SEL_IN_OVL0),
MMSYS_ROUTE(OVL, 0, RDMA, 0,
DISP_REG_CONFIG_DISP_OVL_MOUT_EN, OVL_MOUT_EN_RDMA,
OVL_MOUT_EN_RDMA),
MMSYS_ROUTE(OVL, 1, COLOR, 1,
DISP_REG_CONFIG_DISP_OVL1_MOUT_EN, OVL1_MOUT_EN_COLOR1,
OVL1_MOUT_EN_COLOR1),
MMSYS_ROUTE(OVL, 1, COLOR, 1,
DISP_REG_CONFIG_DISP_COLOR1_SEL_IN, COLOR1_SEL_IN_OVL1,
COLOR1_SEL_IN_OVL1),
MMSYS_ROUTE(RDMA, 0, DPI, 0,
DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
RDMA0_SOUT_DPI0),
MMSYS_ROUTE(RDMA, 0, DPI, 1,
DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
RDMA0_SOUT_DPI1),
MMSYS_ROUTE(RDMA, 0, DSI, 1,
DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
RDMA0_SOUT_DSI1),
MMSYS_ROUTE(RDMA, 0, DSI, 2,
DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
RDMA0_SOUT_DSI2),
MMSYS_ROUTE(RDMA, 0, DSI, 3,
DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN, RDMA0_SOUT_MASK,
RDMA0_SOUT_DSI3),
MMSYS_ROUTE(RDMA, 1, DPI, 0,
DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
RDMA1_SOUT_DPI0),
MMSYS_ROUTE(RDMA, 1, DPI, 0,
DISP_REG_CONFIG_DPI_SEL_IN, DPI0_SEL_IN_MASK,
DPI0_SEL_IN_RDMA1),
MMSYS_ROUTE(RDMA, 1, DPI, 1,
DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
RDMA1_SOUT_DPI1),
MMSYS_ROUTE(RDMA, 1, DPI, 1,
DISP_REG_CONFIG_DPI_SEL_IN, DPI1_SEL_IN_MASK,
DPI1_SEL_IN_RDMA1),
MMSYS_ROUTE(RDMA, 1, DSI, 0,
DISP_REG_CONFIG_DSIE_SEL_IN, DSI0_SEL_IN_MASK,
DSI0_SEL_IN_RDMA1),
MMSYS_ROUTE(RDMA, 1, DSI, 1,
DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
RDMA1_SOUT_DSI1),
MMSYS_ROUTE(RDMA, 1, DSI, 1,
DISP_REG_CONFIG_DSIO_SEL_IN, DSI1_SEL_IN_MASK,
DSI1_SEL_IN_RDMA1),
MMSYS_ROUTE(RDMA, 1, DSI, 2,
DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
RDMA1_SOUT_DSI2),
MMSYS_ROUTE(RDMA, 1, DSI, 2,
DISP_REG_CONFIG_DSIE_SEL_IN, DSI2_SEL_IN_MASK,
DSI2_SEL_IN_RDMA1),
MMSYS_ROUTE(RDMA, 1, DSI, 3,
DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN, RDMA1_SOUT_MASK,
RDMA1_SOUT_DSI3),
MMSYS_ROUTE(RDMA, 1, DSI, 3,
DISP_REG_CONFIG_DSIO_SEL_IN, DSI3_SEL_IN_MASK,
DSI3_SEL_IN_RDMA1),
MMSYS_ROUTE(RDMA, 2, DPI, 0,
DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
RDMA2_SOUT_DPI0),
MMSYS_ROUTE(RDMA, 2, DPI, 0,
DISP_REG_CONFIG_DPI_SEL_IN, DPI0_SEL_IN_MASK,
DPI0_SEL_IN_RDMA2),
MMSYS_ROUTE(RDMA, 2, DPI, 1,
DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
RDMA2_SOUT_DPI1),
MMSYS_ROUTE(RDMA, 2, DPI, 1,
DISP_REG_CONFIG_DPI_SEL_IN, DPI1_SEL_IN_MASK,
DPI1_SEL_IN_RDMA2),
MMSYS_ROUTE(RDMA, 2, DSI, 0,
DISP_REG_CONFIG_DSIE_SEL_IN, DSI0_SEL_IN_MASK,
DSI0_SEL_IN_RDMA2),
MMSYS_ROUTE(RDMA, 2, DSI, 1,
DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
RDMA2_SOUT_DSI1),
MMSYS_ROUTE(RDMA, 2, DSI, 1,
DISP_REG_CONFIG_DSIO_SEL_IN, DSI1_SEL_IN_MASK,
DSI1_SEL_IN_RDMA2),
MMSYS_ROUTE(RDMA, 2, DSI, 2,
DISP_REG_CONFIG_DISP_RDMA2_SOUT, RDMA2_SOUT_MASK,
RDMA2_SOUT_DSI2),
MMSYS_ROUTE(RDMA, 2, DSI, 2,
DISP_REG_CONFIG_DSIE_SEL_IN, DSI2_SEL_IN_MASK,
DSI2_SEL_IN_RDMA2),
};
#endif /* __SOC_MEDIATEK_MTK_MMSYS_H */

7
drivers/soc/mediatek/mtk-socinfo.c
View File

@@ -76,11 +76,14 @@ static int mtk_socinfo_create_socinfo_node(struct mtk_socinfo *mtk_socinfop)
if (!attrs)
return -ENOMEM;
if (data->marketing_name != NULL && data->marketing_name[0] != '\0')
if (data->marketing_name != NULL && data->marketing_name[0] != '\0') {
attrs->family = devm_kasprintf(mtk_socinfop->dev, GFP_KERNEL, "MediaTek %s",
data->marketing_name);
else
if (!attrs->family)
return -ENOMEM;
} else {
attrs->family = soc_manufacturer;
}
attrs->soc_id = data->soc_name;
/*