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ASoC: Add TAS67524 quad-channel Class-D amplifier driver

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Sen Wang <sen@ti.com> says:

This series adds support for the TI TAS675x (TAS6754, TAS67524)
quad-channel automotive Class-D amplifiers. The devices have an
integrated DSP and load diagnostics, and are controlled over I2C.

Patch 1 adds the dt-binding, patch 2 the codec driver, patch 3 the
ALSA mixer controls documentation, and patch 4 adds the MAINTAINERS
entry.

Tested on AM62D-EVM with a TAS67CD-AEC daughter card. For setup &
test procedures, refer to the GitHub repository.

GitHub: https://github.com/SenWang125/tas67-linux
This commit is contained in:
Mark Brown
2026-04-27 08:36:18 +09:00
parent eb0d565514 3507e568d6
commit a960faa424
7 changed files with 3679 additions and 0 deletions
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280
Documentation/devicetree/bindings/sound/ti,tas67524.yaml Normal file
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/sound/ti,tas67524.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Texas Instruments TAS67524 Audio Amplifier
maintainers:
- Sen Wang <sen@ti.com>
description:
The TAS67524 is a four-channel, digital-input, automotive
Class-D audio amplifier with load diagnostics and an integrated
DSP for audio processing.
allOf:
- $ref: dai-common.yaml#
properties:
compatible:
oneOf:
- items:
- enum:
- ti,tas6754
- const: ti,tas67524
- const: ti,tas67524
reg:
maxItems: 1
'#sound-dai-cells':
const: 1
description: |
The device exposes three DAIs, selected by index.
0 - Standard Audio Path (Playback)
1 - Low-Latency Playback Path (Playback)
2 - Sensory Feedback (Capture - Vpredict and Isense)
By default, all four channels of each DAI are active.
interrupts:
maxItems: 1
description:
Active-low falling-edge interrupt from the FAULT pin. When provided,
the driver uses IRQ-driven fault reporting instead of polling.
powerdown-gpios:
maxItems: 1
description:
GPIO connected to the PD pin, active low. Controls the internal
digital circuitry power state. When asserted the device enters
full power-down mode and all register state is lost. Can be omitted if
PD pin is hardwired or externally controlled.
standby-gpios:
maxItems: 1
description:
GPIO connected to the STBY pin, active low. Controls the analog
power stage. When asserted the device enters Deep Sleep mode but
remains I2C-accessible with registers retained. Can be omitted if
STBY pin is tied to PD or hardwired.
dvdd-supply:
description:
Digital logic supply (1.62 V to 3.6 V). All three supply rails must
be within their recommended operating ranges before the PD pin is
released.
pvdd-supply:
description:
Output FET power supply (4.5 V to 19 V). All three supply rails must
be within their recommended operating ranges before the PD pin is
released.
vbat-supply:
description:
Battery supply for the Class-D output stage (4.5 V to 19 V). Optional
when PVDD and VBAT are connected to the same supply rail. When absent,
VBAT is assumed hardwired to PVDD.
ti,fast-boot:
type: boolean
description:
Skip DC load diagnostic sweep at power-on to reduce boot latency.
Automatic diagnostics after fault conditions remain enabled. Hardware
overcurrent protection is always active.
ti,audio-slot-no:
$ref: /schemas/types.yaml#/definitions/uint32
description:
TDM slot offset for the standard audio playback path via SDIN1. A value
of 4 maps to slot 4. If omitted, slot assignment is derived from the
tx_mask provided via set_tdm_slot(). Without either property, no slot
mapping is configured.
ti,llp-slot-no:
$ref: /schemas/types.yaml#/definitions/uint32
description:
TDM slot offset for the low-latency playback path via SDIN1. If omitted,
slot assignment is derived from the tx_mask provided via set_tdm_slot().
Without either property, no slot mapping is configured. Disabled outside
of LLP mode, and only relevant for TDM formats.
ti,vpredict-slot-no:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
In TDM mode, enables Vpredict output and assigns its starting slot;
four consecutive slots carry Vpredict Ch1-4 on SDOUT1. May coexist
with ti,isense-slot-no using separate non-overlapping slots.
In I2S mode, enables Vpredict output on SDOUT1 (Ch1/Ch2) and SDOUT2
(Ch3/Ch4). The slot value is unused. Requires a GPIO configured as
sdout2 for Ch3/Ch4; without it only Ch1/Ch2 are output. Mutually
exclusive with ti,isense-slot-no; if both are set, Vpredict takes
priority.
Irrelevant in Left-J and Right-J modes.
ti,isense-slot-no:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
In TDM mode, enables Isense output and assigns its starting slot;
four consecutive slots carry Isense Ch1-4 on SDOUT1. May coexist
with ti,vpredict-slot-no using separate non-overlapping slots.
In I2S mode, enables Isense output on SDOUT1 (Ch1/Ch2) and SDOUT2
(Ch3/Ch4). The slot value is unused. Requires a GPIO configured as
SDOUT2 for Ch3/Ch4; without it only Ch1/Ch2 are output. Mutually
exclusive with ti,vpredict-slot-no; Vpredict takes priority if both
are set.
Irrelevant in Left-J and Right-J modes.
ti,gpio1-function:
$ref: /schemas/types.yaml#/definitions/string
description:
Function for the GPIO_1 pin. When omitted, GPIO_1 remains in its
power-on default state.
enum:
- low # Output: driven low
- auto-mute # Output: high when all channels are auto-muted
- auto-mute-ch4 # Output: high when channel 4 is auto-muted
- auto-mute-ch3 # Output: high when channel 3 is auto-muted
- auto-mute-ch2 # Output: high when channel 2 is auto-muted
- auto-mute-ch1 # Output: high when channel 1 is auto-muted
- sdout2 # Output: Routes secondary serial data output 2
- sdout1 # Output: Re-routes secondary serial data output 1
- warn # Output: warning signal (OTW, CBC)
- fault # Output: fault signal (OTSD, OC, DC)
- clock-sync # Output: clock synchronisation
- invalid-clock # Output: high when clock is invalid
- high # Output: driven high
- mute # Input: external mute control
- phase-sync # Input: phase synchronisation
- sdin2 # Input: secondary SDIN2 for I2S/LJ/RJ ch3/ch4
- deep-sleep # Input: asserted transitions device to Deep Sleep
- hiz # Input: asserted transitions device to Hi-Z
- play # Input: asserted transitions device to Play
- sleep # Input: asserted transitions device to Sleep
ti,gpio2-function:
$ref: /schemas/types.yaml#/definitions/string
description:
Function for the GPIO_2 pin. When omitted, GPIO_2 remains in its
power-on default state.
enum:
- low # Output: driven low
- auto-mute # Output: high when all channels are auto-muted
- auto-mute-ch4 # Output: high when channel 4 is auto-muted
- auto-mute-ch3 # Output: high when channel 3 is auto-muted
- auto-mute-ch2 # Output: high when channel 2 is auto-muted
- auto-mute-ch1 # Output: high when channel 1 is auto-muted
- sdout2 # Output: Routes secondary serial data output 2
- sdout1 # Output: Re-routes secondary serial data output 1
- warn # Output: warning signal (OTW, CBC)
- fault # Output: fault signal (OTSD, OC, DC)
- clock-sync # Output: clock synchronisation
- invalid-clock # Output: high when clock is invalid
- high # Output: driven high
- mute # Input: external mute control
- phase-sync # Input: phase synchronisation
- sdin2 # Input: secondary SDIN2 for I2S/LJ/RJ ch3/ch4
- deep-sleep # Input: asserted transitions device to Deep Sleep
- hiz # Input: asserted transitions device to Hi-Z
- play # Input: asserted transitions device to Play
- sleep # Input: asserted transitions device to Sleep
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
$ref: audio-graph-port.yaml#
unevaluatedProperties: false
description: Standard audio playback port (DAI 0).
port@1:
$ref: audio-graph-port.yaml#
unevaluatedProperties: false
description: Low-latency playback port (LLP) (DAI 1).
port@2:
$ref: audio-graph-port.yaml#
unevaluatedProperties: false
description: Sensory feedback capture port (DAI 2).
port:
$ref: audio-graph-port.yaml#
unevaluatedProperties: false
required:
- compatible
- reg
- '#sound-dai-cells'
- dvdd-supply
- pvdd-supply
anyOf:
- required: [powerdown-gpios]
- required: [standby-gpios]
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
amplifier@70 {
compatible = "ti,tas67524";
reg = <0x70>;
#sound-dai-cells = <1>;
sound-name-prefix = "TAS0";
standby-gpios = <&main_gpio0 33 GPIO_ACTIVE_LOW>;
dvdd-supply = <&dvdd_1v8>;
pvdd-supply = <&pvdd_12v>;
vbat-supply = <&vbat_12v>;
ti,audio-slot-no = <0>;
ti,llp-slot-no = <4>;
ti,vpredict-slot-no = <0>;
ti,isense-slot-no = <4>;
ti,gpio2-function = "warn";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
tas0_audio_ep: endpoint {
dai-format = "dsp_b";
remote-endpoint = <&be_tas0_audio_ep>;
};
};
port@1 {
reg = <1>;
tas0_anc_ep: endpoint {
remote-endpoint = <&be_tas0_anc_ep>;
};
};
port@2 {
reg = <2>;
tas0_fb_ep: endpoint {
remote-endpoint = <&be_tas0_fb_ep>;
};
};
};
};
};

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.. SPDX-License-Identifier: GPL-2.0
======================================
TAS675x Codec Mixer Controls
======================================
This document describes the ALSA mixer controls for the TAS675x
4-channel amplifier driver.
For device tree bindings, see:
Documentation/devicetree/bindings/sound/ti,tas67524.yaml
DSP Signal Path Mode
====================
DSP Signal Path Mode
--------------------
:Description: Signal processing mode selection.
:Type: Enumerated
:Default: Normal
:Options: Normal, LLP, FFLP
:Register: 0x32 bits [1:0]
Normal
Full DSP with all features available.
LLP (Low Latency Path)
Bypasses DSP processing. DSP protection features (Thermal Foldback,
PVDD Foldback, Clip Detect) and Real-Time Load Diagnostics unavailable.
FFLP (Full Feature Low Latency Path)
Reduced latency. Real-Time Load Diagnostics unavailable.
The following controls are unavailable in LLP mode:
``Thermal Foldback Switch``, ``PVDD Foldback Switch``,
``DC Blocker Bypass Switch``, ``Clip Detect Switch``, ``Audio SDOUT Switch``.
The following controls require Normal mode (unavailable in FFLP and LLP):
``CHx RTLDG Switch``, ``RTLDG Clip Mask Switch``, ``ISENSE Calibration Switch``,
``RTLDG Open Load Threshold``, ``RTLDG Short Load Threshold``,
``CHx RTLDG Impedance``.
Volume Controls
===============
Analog Playback Volume
----------------------
:Description: Analog output gain for all channels (CH1/CH2 and CH3/CH4 pairs).
:Type: Volume (TLV)
:Default: 0 dB
:Range: -15.5 dB to 0 dB (0.5 dB steps)
:Register: 0x4A (CH1/CH2), 0x4B (CH3/CH4)
Analog Gain Ramp Step
---------------------
:Description: Anti-pop ramp step duration for analog gain transitions.
:Type: Enumerated
:Default: 15us
:Options: 15us, 60us, 200us, 400us
:Register: 0x4E bits [3:2]
CHx Digital Playback Volume
---------------------------
:Description: Per-channel digital volume control (x = 1, 2, 3, 4).
:Type: Volume (TLV)
:Default: 0 dB
:Range: -103 dB to 0 dB (0.5 dB steps)
:Bounds: 0x30 (min/mute) to 0xFF (max)
:Register: 0x40 (CH1), 0x41 (CH2), 0x42 (CH3), 0x43 (CH4)
Volume Ramp Down Rate
---------------------
:Description: Update frequency during mute transition.
:Type: Enumerated
:Default: 16 FS
:Options: 4 FS, 16 FS, 32 FS, Instant
:Register: 0x44 bits [7:6]
Volume Ramp Down Step
---------------------
:Description: dB change per update during mute.
:Type: Enumerated
:Default: 0.5dB
:Options: 4dB, 2dB, 1dB, 0.5dB
:Register: 0x44 bits [5:4]
Volume Ramp Up Rate
-------------------
:Description: Update frequency during unmute transition.
:Type: Enumerated
:Default: 16 FS
:Options: 4 FS, 16 FS, 32 FS, Instant
:Register: 0x44 bits [3:2]
Volume Ramp Up Step
-------------------
:Description: dB change per update during unmute.
:Type: Enumerated
:Default: 0.5dB
:Options: 4dB, 2dB, 1dB, 0.5dB
:Register: 0x44 bits [1:0]
CH1/2 Volume Combine
--------------------
:Description: Links digital volume controls for CH1 and CH2.
:Type: Enumerated
:Default: Independent
:Options: Independent, CH2 follows CH1, CH1 follows CH2
:Register: 0x46 bits [1:0]
CH3/4 Volume Combine
--------------------
:Description: Links digital volume controls for CH3 and CH4.
:Type: Enumerated
:Default: Independent
:Options: Independent, CH4 follows CH3, CH3 follows CH4
:Register: 0x46 bits [3:2]
Auto Mute & Silence Detection
==============================
CHx Auto Mute Switch
--------------------
:Description: Enables automatic muting on zero-signal detection (x = 1, 2, 3, 4).
:Type: Boolean Switch
:Default: Disabled (0)
:Register: 0x47 bit [0] (CH1), bit [1] (CH2), bit [2] (CH3), bit [3] (CH4)
Auto Mute Combine Switch
------------------------
:Description: Coordinated muting behaviour across all channels.
:Type: Boolean Switch
:Default: Disabled (0)
:Behavior: Disabled: channels mute independently when their signal is zero.
Enabled: all channels mute together only when all detect zero
signal; unmute when any channel has non-zero signal.
:Register: 0x47 bit [4]
CHx Auto Mute Time
------------------
:Description: Duration of zero signal before muting triggers (x = 1, 2, 3, 4).
:Type: Enumerated
:Default: 11.5ms
:Options: 11.5ms, 53ms, 106.5ms, 266.5ms, 535ms, 1065ms, 2665ms, 5330ms
:Register: 0x48 bits [7:4] (CH1), bits [3:0] (CH2),
0x49 bits [7:4] (CH3), bits [3:0] (CH4)
:Note: Values are at 96 kHz. At 48 kHz, times are doubled.
Clock & EMI Management
======================
Spread Spectrum Mode
--------------------
:Description: Frequency dithering mode to reduce peak EMI.
:Type: Enumerated
:Default: Disabled
:Options: Disabled, Triangle, Random, Triangle and Random
:Register: 0x61 bits [1:0]
SS Triangle Range
-----------------
:Description: Frequency deviation range for Triangle spread spectrum.
:Type: Enumerated
:Default: 6.5%
:Options: 6.5%, 13.5%, 5%, 10%
:Register: 0x62 bits [1:0]
:Note: Applies only when Spread Spectrum Mode includes Triangle.
SS Random Range
---------------
:Description: Frequency deviation range for Random spread spectrum.
:Type: Enumerated
:Default: 0.83%
:Options: 0.83%, 2.50%, 5.83%, 12.50%, 25.83%
:Register: 0x62 bits [6:4]
:Note: Applies only when Spread Spectrum Mode includes Random.
SS Random Dwell Range
---------------------
:Description: Dwell time range for Random spread spectrum (FSS = spread
spectrum modulation frequency).
:Type: Enumerated
:Default: 1/FSS to 2/FSS
:Options: 1/FSS to 2/FSS, 1/FSS to 4/FSS, 1/FSS to 8/FSS, 1/FSS to 15/FSS
:Register: 0x62 bits [3:2]
:Note: Applies only when Spread Spectrum Mode includes Random.
SS Triangle Dwell Min
---------------------
:Description: Minimum dwell time at Triangle spread spectrum frequency extremes.
:Type: Integer
:Default: 0
:Range: 0 to 15 (0 = feature disabled)
:Register: 0x66 bits [7:4]
:Note: Counts in FSS clock cycles. The modulator holds the extreme
frequency for at least this many FSS cycles before reversing.
When Dwell Min equals Dwell Max, the dwell feature is inactive.
For FSS values at each PWM frequency refer to the "Spread
Spectrum" section of the TRM.
SS Triangle Dwell Max
---------------------
:Description: Maximum dwell time at Triangle spread spectrum frequency extremes.
:Type: Integer
:Default: 0
:Range: 0 to 15 (0 = feature disabled)
:Register: 0x66 bits [3:0]
:Note: Counts in FSS clock cycles. Must be >= Dwell Min. When Dwell Max
equals Dwell Min, the dwell feature is inactive.
Hardware Protection
===================
OTSD Auto Recovery Switch
--------------------------
:Description: Enables automatic recovery from over-temperature shutdown.
:Type: Boolean Switch
:Default: Disabled (0)
:Register: 0x8F bit [1]
:Note: When disabled, manual fault clearing is required after OTSD events.
Overcurrent Limit Level
-----------------------
:Description: Current-limit trip point sensitivity.
:Type: Enumerated
:Default: Level 4
:Options: Level 4, Level 3, Level 2, Level 1
:Register: 0x55 bits [1:0]
:Note: Level 4 is the least sensitive (highest trip current); Level 1 is
the most sensitive. The exact ILIM values depend on operating
conditions (PVDD voltage, switching frequency, and temperature).
Refer to the Electrical Characteristics table and the
"Overcurrent Limit (Cycle-By-Cycle)" section of the TRM.
CHx OTW Threshold
-----------------
:Description: Over-temperature warning threshold per channel (x = 1, 2, 3, 4).
:Type: Enumerated
:Default: >95C
:Options: Disabled, >95C, >110C, >125C, >135C, >145C, >155C, >165C
:Register: 0xE2 bits [6:4] (CH1), bits [2:0] (CH2),
0xE3 bits [6:4] (CH3), bits [2:0] (CH4)
Temperature and Voltage Monitoring
===================================
PVDD Sense
----------
:Description: Supply voltage sense register.
:Type: Integer (read-only)
:Range: 0 to 255
:Conversion: value × 0.19 V
:Register: 0x74
Global Temperature
------------------
:Description: Global die temperature sense register.
:Type: Integer (read-only)
:Range: 0 to 255
:Conversion: (value × 0.5 °C) − 50 °C
:Register: 0x75
CHx Temperature Range
---------------------
:Description: Per-channel coarse temperature range indicator (x = 1, 2, 3, 4).
:Type: Integer (read-only)
:Range: 0 to 3
:Mapping: 0 = <80 °C, 1 = 80–100 °C, 2 = 100–120 °C, 3 = >120 °C
:Register: 0xBB bits [7:6] (CH1), bits [5:4] (CH2),
0xBC bits [3:2] (CH3), bits [1:0] (CH4)
Load Diagnostics
================
The TAS675x provides three load diagnostic modes:
DC Load Diagnostics (DC LDG)
Measures DC resistance to detect S2G (short-to-ground), S2P
(short-to-power), OL (open load), and SL (shorted load) faults.
AC Load Diagnostics (AC LDG)
Measures complex AC impedance at a configurable frequency. Detects
capacitive loads and tweeter configurations.
Real-Time Load Diagnostics (RTLDG)
Monitors impedance continuously during playback using a pilot tone.
Normal DSP mode only, at 48 kHz or 96 kHz.
Fast Boot Mode
--------------
By default the device runs DC load diagnostics at initialization before
accepting audio. Setting ``ti,fast-boot`` in the device tree bypasses this
initial diagnostic run for faster startup. Automatic diagnostics after
fault recovery remain enabled.
DC Load Diagnostics
-------------------
The ``CHx DC LDG Report`` 4-bit fault field uses the following encoding:
====== =========== ===================================================
Bit Fault Description
====== =========== ===================================================
[3] S2G Short-to-Ground
[2] S2P Short-to-Power
[1] OL Open Load
[0] SL Shorted Load
====== =========== ===================================================
DC LDG Trigger
~~~~~~~~~~~~~~
:Description: Triggers manual DC load diagnostics on all channels.
:Type: Boolean (write-only)
:Note: Returns -EBUSY if any DAI stream (playback or capture) is active.
The driver manages all channel state transitions. Blocks until
diagnostics complete or time out (300 ms).
DC LDG Auto Diagnostics Switch
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
:Description: Enables automatic DC diagnostics after fault recovery.
:Type: Boolean Switch
:Default: Enabled (1)
:Register: 0xB0 bit [0]
:Note: Active-low, when enabled, affected channels re-run diagnostics after
fault recovery and retry approximately every 750 ms until resolved.
CHx LO LDG Switch
~~~~~~~~~~~~~~~~~
:Description: Enables line output load detection per channel (x = 1, 2, 3, 4).
:Type: Boolean Switch
:Default: Disabled (0)
:Register: 0xB1 bit [3] (CH1), bit [2] (CH2), bit [1] (CH3), bit [0] (CH4)
:Note: When enabled and DC diagnostics report OL, the device tests for
a high-impedance line output load.
DC LDG SLOL Ramp Time
~~~~~~~~~~~~~~~~~~~~~
:Description: Voltage ramp time for shorted-load and open-load detection.
:Type: Enumerated
:Default: 15 ms
:Options: 15 ms, 30 ms, 10 ms, 20 ms
:Register: 0xB2 bits [7:6]
DC LDG SLOL Settling Time
~~~~~~~~~~~~~~~~~~~~~~~~~~
:Description: Settling time for shorted-load and open-load detection.
:Type: Enumerated
:Default: 10 ms
:Options: 10 ms, 5 ms, 20 ms, 15 ms
:Register: 0xB2 bits [5:4]
DC LDG S2PG Ramp Time
~~~~~~~~~~~~~~~~~~~~~
:Description: Voltage ramp time for short-to-power and short-to-ground detection.
:Type: Enumerated
:Default: 5 ms
:Options: 5 ms, 2.5 ms, 10 ms, 15 ms
:Register: 0xB2 bits [3:2]
DC LDG S2PG Settling Time
~~~~~~~~~~~~~~~~~~~~~~~~~~
:Description: Settling time for short-to-power and short-to-ground detection.
:Type: Enumerated
:Default: 10 ms
:Options: 10 ms, 5 ms, 20 ms, 30 ms
:Register: 0xB2 bits [1:0]
CHx DC LDG SL Threshold
~~~~~~~~~~~~~~~~~~~~~~~~
:Description: Shorted-load detection threshold per channel (x = 1, 2, 3, 4).
:Type: Enumerated
:Default: 1 Ohm
:Options: 0.5 Ohm, 1 Ohm, 1.5 Ohm, 2 Ohm, 2.5 Ohm,
3 Ohm, 3.5 Ohm, 4 Ohm, 4.5 Ohm, 5 Ohm
:Register: 0xB3 bits [7:4] (CH1), bits [3:0] (CH2),
0xB4 bits [7:4] (CH3), bits [3:0] (CH4)
DC LDG Result
~~~~~~~~~~~~~
:Description: Overall DC diagnostic result register.
:Type: Integer (read-only)
:Range: 0x00 to 0xFF
:Register: 0xC2
:Bit Encoding:
======== =====================================================
Bits Description
======== =====================================================
[7:4] Line output detection result, one bit per channel
[3:0] DC diagnostic pass/fail per channel (1=pass, 0=fail)
======== =====================================================
CHx DC LDG Report
~~~~~~~~~~~~~~~~~
:Description: DC diagnostic fault status per channel (x = 1, 2, 3, 4).
:Type: Integer (read-only)
:Range: 0x0 to 0xF
:Register: 0xC0 bits [7:4] (CH1), bits [3:0] (CH2),
0xC1 bits [7:4] (CH3), bits [3:0] (CH4)
:Note: See fault bit encoding table at the start of this section.
CHx LO LDG Report
~~~~~~~~~~~~~~~~~
:Description: Line output load detection result per channel (x = 1, 2, 3, 4).
:Type: Boolean (read-only)
:Values: 0 = not detected, 1 = line output load detected
:Register: 0xC2 bit [7] (CH1), bit [6] (CH2), bit [5] (CH3), bit [4] (CH4)
CHx DC Resistance
~~~~~~~~~~~~~~~~~
:Description: Measured DC load resistance per channel (x = 1, 2, 3, 4).
:Type: Float (read-only, displayed in ohms)
:Resolution: 0.1 ohm per code (10-bit value)
:Range: 0.0 to 102.3 ohms
:Register: 0xD9 bits [7:6]/[5:4]/[3:2]/[1:0] (MSB for CH1–CH4),
0xDA (CH1 LSB), 0xDB (CH2 LSB), 0xDC (CH3 LSB), 0xDD (CH4 LSB)
AC Load Diagnostics
-------------------
AC LDG Trigger
~~~~~~~~~~~~~~
:Description: Triggers AC impedance measurement on all channels.
:Type: Boolean (write-only)
:Note: Returns -EBUSY if any DAI stream (playback or capture) is active.
The driver transitions all channels to SLEEP state before starting
the measurement. Blocks until diagnostics complete or time out.
AC LDG Gain
~~~~~~~~~~~
:Description: Measurement resolution for AC diagnostics.
:Type: Boolean Switch
:Default: 1 (Gain 8)
:Values: 0 = 0.8 ohm/code (Gain 1), 1 = 0.1 ohm/code (Gain 8)
:Register: 0xB5 bit [4]
:Note: Gain 8 recommended for load impedances below 8 ohms.
AC LDG Test Frequency
~~~~~~~~~~~~~~~~~~~~~
:Description: Test signal frequency for AC impedance measurement.
:Type: Integer
:Default: 200 (0xC8 = 18.75 kHz)
:Range: 0x01 to 0xFF (0x00 reserved)
:Formula: Frequency = 93.75 Hz × register value
:Register: 0xB8
CHx AC LDG Real / CHx AC LDG Imag
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
:Description: Real and imaginary AC impedance components per channel
(x = 1, 2, 3, 4).
:Type: Integer (read-only)
:Range: 0x00 to 0xFF (8-bit signed)
:Register: 0xC3 (CH1 Real), 0xC4 (CH1 Imag), 0xC5 (CH2 Real), 0xC6 (CH2 Imag),
0xC7 (CH3 Real), 0xC8 (CH3 Imag), 0xC9 (CH4 Real), 0xCA (CH4 Imag)
:Note: Scale set by AC LDG Gain.
Speaker Protection & Detection
-------------------------------
Tweeter Detection Switch
~~~~~~~~~~~~~~~~~~~~~~~~
:Description: Enables tweeter detection using the AC impedance magnitude comparator.
:Type: Boolean Switch
:Default: Enabled (1)
:Register: 0xB6 bit [0]
:Note: The underlying register bit is TWEETER DETECT DISABLE (active-low).
Control value 1 = detection enabled (register bit 0), 0 = disabled
(register bit 1).
Tweeter Detect Threshold
~~~~~~~~~~~~~~~~~~~~~~~~~
:Description: Magnitude threshold for tweeter detection.
:Type: Integer
:Default: 0
:Range: 0x00 to 0xFF
:Resolution: 0.8 ohm/code (AC LDG Gain=0) or 0.1 ohm/code (AC LDG Gain=1)
:Register: 0xB7
CHx Tweeter Detect Report
~~~~~~~~~~~~~~~~~~~~~~~~~~
:Description: Tweeter detection result per channel (x = 1, 2, 3, 4).
:Type: Boolean (read-only)
:Values: 0 = no tweeter detected, 1 = tweeter detected
:Register: 0xCB bit [3] (CH1), bit [2] (CH2), bit [1] (CH3), bit [0] (CH4)
DSP Protection Features
=======================
These controls are unavailable in LLP mode.
Thermal Foldback Switch
-----------------------
:Description: Enables dynamic gain reduction based on die temperature.
:Type: Boolean Switch
:Default: Disabled (0)
:Register: 0x3A bit [0]
PVDD Foldback Switch
--------------------
:Description: Enables automatic gain limiting when supply voltage drops
(Automatic Gain Limiter).
:Type: Boolean Switch
:Default: Disabled (0)
:Register: 0x3A bit [4]
DC Blocker Bypass Switch
------------------------
:Description: Bypasses the DC-blocking high-pass filter.
:Type: Boolean Switch
:Default: Not bypassed (0)
:Register: 0x39 bit [0]
Clip Detect Switch
------------------
:Description: Enables DSP-based clip detection (Pseudo-Analog Clip Detect).
:Type: Boolean Switch
:Default: Disabled (0)
:Register: 0x93 bit [6]
Audio SDOUT Switch
------------------
:Description: Routes post-processed audio to the SDOUT pin instead of
Vpredict data.
:Type: Boolean Switch
:Default: Disabled (0)
:Register: 0x3A bit [5]
:Note: When enabled, replaces Vpredict data on SDOUT with post-processed
SDIN. All SDOUT configurations that apply to Vpredict also apply
to SDIN-to-SDOUT transmission.
Real-Time Load Diagnostics
===========================
These controls require Normal DSP mode at 48 kHz or 96 kHz. They are
unavailable at 192 kHz and in FFLP and LLP modes.
CHx RTLDG Switch
----------------
:Description: Enables real-time impedance monitoring during playback
(x = 1, 2, 3, 4).
:Type: Boolean Switch
:Default: Disabled (0)
:Register: 0x37 bit [3] (CH1), bit [2] (CH2), bit [1] (CH3), bit [0] (CH4)
RTLDG Clip Mask Switch
----------------------
:Description: Suppresses impedance updates during clipping events.
:Type: Boolean Switch
:Default: Enabled (1)
:Register: 0x37 bit [4]
ISENSE Calibration Switch
--------------------------
:Description: Enables current sense calibration for accurate impedance
measurements.
:Type: Boolean Switch
:Default: Disabled (0)
:Register: 0x5B bit [3]
RTLDG Open Load Threshold
--------------------------
:Description: DSP coefficient for open load fault detection threshold.
:Type: DSP coefficient (extended control)
:Register: DSP Book 0x8C, page 0x22, 0x98
RTLDG Short Load Threshold
---------------------------
:Description: DSP coefficient for shorted load fault detection threshold.
:Type: DSP coefficient (extended control)
:Register: DSP Book 0x8C, page 0x22, 0x9C
CHx RTLDG Impedance
-------------------
:Description: Real-time load impedance per channel (x = 1, 2, 3, 4).
:Type: Float (read-only, displayed in ohms)
:Register: 0xD1–0xD2 (CH1), 0xD3–0xD4 (CH2), 0xD5–0xD6 (CH3), 0xD7–0xD8 (CH4)
:Note: Valid only during PLAY state with RTLDG enabled at 48 or
96 kHz. Holds stale data in SLEEP, MUTE, or Hi-Z states.
Fault Monitoring
================
The driver monitors faults via IRQ or periodic polling (fallback when
no ``interrupts`` DT property is present). Detected faults are logged
and cleared so affected channels can recover.
Kernel log messages use the format::
tas675x <addr>: <Name> Latched: 0x<value>
Critical faults are logged at ``CRIT`` level; warnings at ``WARN``.
The following fault registers are monitored:
Critical Faults
---------------
These faults place affected channels into the FAULT state. The driver
issues fault clear (register 0x01 bit 3) to allow recovery.
Overtemperature Shutdown (0x87)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
======== ==========================================
Bits Description
======== ==========================================
[4] Global OTSD
[3:0] CH1-CH4 OTSD respectively
======== ==========================================
Fires when die temperature exceeds the OTSD threshold. If auto-recovery
is enabled (``OTSD Auto Recovery Switch``), channels return to their
previous state after cooling. Otherwise fault clear is required.
Overcurrent / DC Fault (0x8E)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
======== ==========================================
Bits Description
======== ==========================================
[7:4] Overcurrent Shutdown, CH1-CH4 respectively
[3:0] DC Fault, CH1-CH4 respectively
======== ==========================================
Overcurrent shutdown occurs when output current reaches the shutdown
threshold (e.g. output short to GND). DC fault fires when DC offset
exceeds the DCFAULT threshold.
Real-Time Load Diagnostic Fault (0x8B)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
======== ==========================================
Bits Description
======== ==========================================
[7:4] Shorted Load faults, CH1-CH4 respectively
[3:0] Open Load faults, CH1-CH4 respectively
======== ==========================================
Reported during playback when RTLDG detects impedance outside the
configured open/short thresholds. Requires RTLDG and current sense to
be enabled, and a sampling rate of 48 kHz or 96 kHz.
CBC Fault/Warning (0x8D)
~~~~~~~~~~~~~~~~~~~~~~~~
======== ==========================================
Bits Description
======== ==========================================
[7:4] Load current warning, CH1-CH4 respectively
[3:0] Load current fault, CH1-CH4 respectively
======== ==========================================
Cycle-by-cycle current limiting events. A warning fires when the
current limit is active for at least 25% of a 21.3 ms window. A fault
fires if the warning persists for 170.4 ms continuously.
Warnings
--------
These conditions are logged but do not place channels into FAULT state.
Corresponding register bits are cleared when read. Nonetheless, the driver
still clears all events as warnings also latch the (mapped) FAULT pin.
Power Fault (0x86)
~~~~~~~~~~~~~~~~~~
======== ==========================================
Bits Description
======== ==========================================
[7] DVDD Power-On-Reset
[4] DVDD Undervoltage
[3] PVDD Overvoltage
[2] VBAT Overvoltage
[1] PVDD Undervoltage
[0] VBAT Undervoltage
======== ==========================================
Supply-related events. DVDD POR at bit 7 is expected after every
power-up and can be ignored.
CP / OUTM Soft Short Fault (0x7D)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
======== ==========================================
Bits Description
======== ==========================================
[5:2] OUTM soft short, CH4-CH1 respectively
[1] Charge Pump UVLO (latched)
[0] Charge Pump UVLO (unlatched/live status)
======== ==========================================
Per-channel out_minus soft short faults and charge pump undervoltage lockout.
Clock Fault (0x8A)
~~~~~~~~~~~~~~~~~~
======== ==========================================
Bits Description
======== ==========================================
[0] Clock error
======== ==========================================
Fires on clock halt or unsupported SCLK/FSYNC ratio. Only logged when
a stream is active (suppressed during idle to avoid noise from normal
stream stop/start transitions). See `Clock Fault Behaviour`_ below.
Overtemperature Warning (0x88)
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
======== ==========================================
Bits Description
======== ==========================================
[4] Global OTW
[3:0] CH1-CH4 OTW respectively
======== ==========================================
Fires when temperature crosses the OTW threshold. The device continues
to operate. Only logged on change to avoid log spam.
Clip Warning (0x89)
~~~~~~~~~~~~~~~~~~~
======== ==========================================
Bits Description
======== ==========================================
[3:0] CH1-CH4 clip detected respectively
======== ==========================================
Fires when the audio signal magnitude exceeds the clip detection
threshold. Requires Clip Detect to be enabled. Only logged when a
stream is active.
Driver Known Limitations
========================
Clock Fault Behaviour
---------------------
On Stream Stop
~~~~~~~~~~~~~~
Every time a playback stream stops the FAULT pin briefly asserts. The
ASoC PCM trigger stop sequence calls DAIs in reverse order, so the CPU
DAI stops SCLK before the codec can transition to sleep. The device
detects the clock halt and latches ``CLK_FAULT_LATCHED``, which asserts
the FAULT pin. The driver clears the latch in the ``mute_stream``
callback that follows, so the FAULT pin flicker lasts only a few
milliseconds. Audio output is not affected and no kernel log message
is produced.
On Rapid Rate Switching
~~~~~~~~~~~~~~~~~~~~~~~
When streams are started in rapid succession, an intermittent
``Clock Fault Latched: 0x01`` message may appear in the kernel log.
A (conservative) ~0.5 second gap between sessions eliminates this.
References
==========
- TAS675x Technical Reference Manual: SLOU589A
- Device Tree Bindings: Documentation/devicetree/bindings/sound/ti,tas67524.yaml
- ALSA Control Name Conventions: Documentation/sound/designs/control-names.rst

4
MAINTAINERS
View File

@@ -26321,17 +26321,20 @@ TEXAS INSTRUMENTS AUDIO (ASoC/HDA) DRIVERS
M: Shenghao Ding <shenghao-ding@ti.com>
M: Kevin Lu <kevin-lu@ti.com>
M: Baojun Xu <baojun.xu@ti.com>
M: Sen Wang <sen@ti.com>
L: linux-sound@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/sound/ti,tas2552.yaml
F: Documentation/devicetree/bindings/sound/ti,tas2562.yaml
F: Documentation/devicetree/bindings/sound/ti,tas2770.yaml
F: Documentation/devicetree/bindings/sound/ti,tas27xx.yaml
F: Documentation/devicetree/bindings/sound/ti,tas67524.yaml
F: Documentation/devicetree/bindings/sound/ti,tpa6130a2.yaml
F: Documentation/devicetree/bindings/sound/ti,pcm1681.yaml
F: Documentation/devicetree/bindings/sound/ti,pcm3168a.yaml
F: Documentation/devicetree/bindings/sound/ti,tlv320*.yaml
F: Documentation/devicetree/bindings/sound/ti,tlv320adcx140.yaml
F: Documentation/sound/codecs/tas675x*
F: include/sound/tas2*.h
F: include/sound/tlv320*.h
F: sound/hda/codecs/side-codecs/tas2781_hda_i2c.c
@@ -26345,6 +26348,7 @@ F: sound/soc/codecs/pcm3168a*.*
F: sound/soc/codecs/pcm5102a.c
F: sound/soc/codecs/pcm512x*.*
F: sound/soc/codecs/tas2*.*
F: sound/soc/codecs/tas675x*.*
F: sound/soc/codecs/tlv320*.*
F: sound/soc/codecs/tpa6130a2.*

12
sound/soc/codecs/Kconfig
View File

@@ -275,6 +275,7 @@ config SND_SOC_ALL_CODECS
imply SND_SOC_TAS571X
imply SND_SOC_TAS5720
imply SND_SOC_TAS6424
imply SND_SOC_TAS675X
imply SND_SOC_TDA7419
imply SND_SOC_TFA9879
imply SND_SOC_TFA989X
@@ -2237,6 +2238,17 @@ config SND_SOC_TAS6424
Enable support for Texas Instruments TAS6424 high-efficiency
digital input quad-channel Class-D audio power amplifiers.
config SND_SOC_TAS675X
tristate "Texas Instruments TAS675x Quad-Channel Audio Amplifier"
depends on I2C
select REGMAP_I2C
help
Enable support for Texas Instruments TAS675x quad-channel Class-D
audio power amplifiers (TAS6754, TAS67524). The devices support I2S
and TDM interfaces with real-time voltage and current sense feedback
via SDOUT, and provide DC/AC/real-time load diagnostics for speaker
monitoring.
config SND_SOC_TDA7419
tristate "ST TDA7419 audio processor"
depends on I2C

2
sound/soc/codecs/Makefile
View File

@@ -318,6 +318,7 @@ snd-soc-tas571x-y := tas571x.o
snd-soc-tas5720-y := tas5720.o
snd-soc-tas5805m-y := tas5805m.o
snd-soc-tas6424-y := tas6424.o
snd-soc-tas675x-y := tas675x.o
snd-soc-tda7419-y := tda7419.o
snd-soc-tas2770-y := tas2770.o
snd-soc-tas2781-comlib-y := tas2781-comlib.o
@@ -760,6 +761,7 @@ obj-$(CONFIG_SND_SOC_TAS571X) += snd-soc-tas571x.o
obj-$(CONFIG_SND_SOC_TAS5720) += snd-soc-tas5720.o
obj-$(CONFIG_SND_SOC_TAS5805M) += snd-soc-tas5805m.o
obj-$(CONFIG_SND_SOC_TAS6424) += snd-soc-tas6424.o
obj-$(CONFIG_SND_SOC_TAS675X) += snd-soc-tas675x.o
obj-$(CONFIG_SND_SOC_TDA7419) += snd-soc-tda7419.o
obj-$(CONFIG_SND_SOC_TAS2770) += snd-soc-tas2770.o
obj-$(CONFIG_SND_SOC_TFA9879) += snd-soc-tfa9879.o

2194
sound/soc/codecs/tas675x.c Normal file
View File

File diff suppressed because it is too large Load Diff

367
sound/soc/codecs/tas675x.h Normal file
View File

@@ -0,0 +1,367 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* ALSA SoC Texas Instruments TAS675x Quad-Channel Audio Amplifier
*
* Copyright (C) 2026 Texas Instruments Incorporated - https://www.ti.com/
* Author: Sen Wang <sen@ti.com>
*/
#ifndef __TAS675X_H__
#define __TAS675X_H__
/*
* Book 0, Page 0 — Register Addresses
*/
#define TAS675X_PAGE_SIZE 256
#define TAS675X_PAGE_REG(page, reg) ((page) * TAS675X_PAGE_SIZE + (reg))
/* Page Control & Basic Config */
#define TAS675X_PAGE_CTRL_REG 0x00
#define TAS675X_RESET_REG 0x01
#define TAS675X_OUTPUT_CTRL_REG 0x02
#define TAS675X_STATE_CTRL_CH1_CH2_REG 0x03
#define TAS675X_STATE_CTRL_CH3_CH4_REG 0x04
#define TAS675X_ISENSE_CTRL_REG 0x05
#define TAS675X_DC_DETECT_CTRL_REG 0x06
/* Serial Audio Port */
#define TAS675X_SCLK_INV_CTRL_REG 0x20
#define TAS675X_AUDIO_IF_CTRL_REG 0x21
#define TAS675X_SDIN_CTRL_REG 0x23
#define TAS675X_SDOUT_CTRL_REG 0x25
#define TAS675X_SDIN_OFFSET_MSB_REG 0x27
#define TAS675X_SDIN_AUDIO_OFFSET_REG 0x28
#define TAS675X_SDIN_LL_OFFSET_REG 0x29
#define TAS675X_SDIN_CH_SWAP_REG 0x2A
#define TAS675X_SDOUT_OFFSET_MSB_REG 0x2C
#define TAS675X_VPREDICT_OFFSET_REG 0x2D
#define TAS675X_ISENSE_OFFSET_REG 0x2E
#define TAS675X_SDOUT_EN_REG 0x31
#define TAS675X_LL_EN_REG 0x32
/* DSP & Core Audio Control */
#define TAS675X_RTLDG_EN_REG 0x37
#define TAS675X_DC_BLOCK_BYP_REG 0x39
#define TAS675X_DSP_CTRL_REG 0x3A
#define TAS675X_PAGE_AUTO_INC_REG 0x3B
/* Volume & Mute */
#define TAS675X_DIG_VOL_CH1_REG 0x40
#define TAS675X_DIG_VOL_CH2_REG 0x41
#define TAS675X_DIG_VOL_CH3_REG 0x42
#define TAS675X_DIG_VOL_CH4_REG 0x43
#define TAS675X_DIG_VOL_RAMP_CTRL_REG 0x44
#define TAS675X_DIG_VOL_COMBINE_CTRL_REG 0x46
#define TAS675X_AUTO_MUTE_EN_REG 0x47
#define TAS675X_AUTO_MUTE_TIMING_CH1_CH2_REG 0x48
#define TAS675X_AUTO_MUTE_TIMING_CH3_CH4_REG 0x49
/* Analog Gain & Power Stage */
#define TAS675X_ANALOG_GAIN_CH1_CH2_REG 0x4A
#define TAS675X_ANALOG_GAIN_CH3_CH4_REG 0x4B
#define TAS675X_ANALOG_GAIN_RAMP_CTRL_REG 0x4E
#define TAS675X_PULSE_INJECTION_EN_REG 0x52
#define TAS675X_CBC_CTRL_REG 0x54
#define TAS675X_CURRENT_LIMIT_CTRL_REG 0x55
#define TAS675X_DAC_CLK_REG 0x5A
#define TAS675X_ISENSE_CAL_REG 0x5B
/* Spread Spectrum & PWM Phase */
#define TAS675X_PWM_PHASE_CTRL_REG 0x60
#define TAS675X_SS_CTRL_REG 0x61
#define TAS675X_SS_RANGE_CTRL_REG 0x62
#define TAS675X_SS_DWELL_CTRL_REG 0x66
#define TAS675X_RAMP_PHASE_CTRL_GPO_REG 0x68
#define TAS675X_PWM_PHASE_M_CTRL_CH1_REG 0x69
#define TAS675X_PWM_PHASE_M_CTRL_CH2_REG 0x6A
#define TAS675X_PWM_PHASE_M_CTRL_CH3_REG 0x6B
#define TAS675X_PWM_PHASE_M_CTRL_CH4_REG 0x6C
/* Status & Reporting */
#define TAS675X_AUTO_MUTE_STATUS_REG 0x71
#define TAS675X_STATE_REPORT_CH1_CH2_REG 0x72
#define TAS675X_STATE_REPORT_CH3_CH4_REG 0x73
#define TAS675X_PVDD_SENSE_REG 0x74
#define TAS675X_TEMP_GLOBAL_REG 0x75
#define TAS675X_FS_MON_REG 0x76
#define TAS675X_SCLK_MON_REG 0x77
#define TAS675X_REPORT_ROUTING_1_REG 0x7C
/* Memory Paging & Book Control */
#define TAS675X_SETUP_REG1 0x7D
#define TAS675X_SETUP_REG2 0x7E
#define TAS675X_BOOK_CTRL_REG 0x7F
/* Fault Status */
#define TAS675X_POWER_FAULT_STATUS_1_REG 0x7D
#define TAS675X_POWER_FAULT_STATUS_2_REG 0x80
#define TAS675X_OT_FAULT_REG 0x81
#define TAS675X_OTW_STATUS_REG 0x82
#define TAS675X_CLIP_WARN_STATUS_REG 0x83
#define TAS675X_CBC_WARNING_STATUS_REG 0x85
/* Latched Fault Registers */
#define TAS675X_POWER_FAULT_LATCHED_REG 0x86
#define TAS675X_OTSD_LATCHED_REG 0x87
#define TAS675X_OTW_LATCHED_REG 0x88
#define TAS675X_CLIP_WARN_LATCHED_REG 0x89
#define TAS675X_CLK_FAULT_LATCHED_REG 0x8A
#define TAS675X_RTLDG_OL_SL_FAULT_LATCHED_REG 0x8B
#define TAS675X_CBC_FAULT_WARN_LATCHED_REG 0x8D
#define TAS675X_OC_DC_FAULT_LATCHED_REG 0x8E
#define TAS675X_OTSD_RECOVERY_EN_REG 0x8F
/* Protection & Routing Controls */
#define TAS675X_REPORT_ROUTING_2_REG 0x90
#define TAS675X_REPORT_ROUTING_3_REG 0x91
#define TAS675X_REPORT_ROUTING_4_REG 0x92
#define TAS675X_CLIP_DETECT_CTRL_REG 0x93
#define TAS675X_REPORT_ROUTING_5_REG 0x94
/* GPIO Pin Configuration */
#define TAS675X_GPIO1_OUTPUT_SEL_REG 0x95
#define TAS675X_GPIO2_OUTPUT_SEL_REG 0x96
#define TAS675X_GPIO_INPUT_SLEEP_HIZ_REG 0x9B
#define TAS675X_GPIO_INPUT_PLAY_SLEEP_REG 0x9C
#define TAS675X_GPIO_INPUT_MUTE_REG 0x9D
#define TAS675X_GPIO_INPUT_SYNC_REG 0x9E
#define TAS675X_GPIO_INPUT_SDIN2_REG 0x9F
#define TAS675X_GPIO_CTRL_REG 0xA0
#define TAS675X_GPIO_INVERT_REG 0xA1
/* Load Diagnostics Config */
#define TAS675X_DC_LDG_CTRL_REG 0xB0
#define TAS675X_DC_LDG_LO_CTRL_REG 0xB1
#define TAS675X_DC_LDG_TIME_CTRL_REG 0xB2
#define TAS675X_DC_LDG_SL_CH1_CH2_CTRL_REG 0xB3
#define TAS675X_DC_LDG_SL_CH3_CH4_CTRL_REG 0xB4
#define TAS675X_AC_LDG_CTRL_REG 0xB5
#define TAS675X_TWEETER_DETECT_CTRL_REG 0xB6
#define TAS675X_TWEETER_DETECT_THRESH_REG 0xB7
#define TAS675X_AC_LDG_FREQ_CTRL_REG 0xB8
#define TAS675X_TEMP_CH1_CH2_REG 0xBB
#define TAS675X_TEMP_CH3_CH4_REG 0xBC
#define TAS675X_WARN_OT_MAX_FLAG_REG 0xBD
/* DC Load Diagnostic Reports */
#define TAS675X_DC_LDG_REPORT_CH1_CH2_REG 0xC0
#define TAS675X_DC_LDG_REPORT_CH3_CH4_REG 0xC1
#define TAS675X_DC_LDG_RESULT_REG 0xC2
#define TAS675X_AC_LDG_REPORT_CH1_R_REG 0xC3
#define TAS675X_AC_LDG_REPORT_CH1_I_REG 0xC4
#define TAS675X_AC_LDG_REPORT_CH2_R_REG 0xC5
#define TAS675X_AC_LDG_REPORT_CH2_I_REG 0xC6
#define TAS675X_AC_LDG_REPORT_CH3_R_REG 0xC7
#define TAS675X_AC_LDG_REPORT_CH3_I_REG 0xC8
#define TAS675X_AC_LDG_REPORT_CH4_R_REG 0xC9
#define TAS675X_AC_LDG_REPORT_CH4_I_REG 0xCA
#define TAS675X_TWEETER_REPORT_REG 0xCB
/* RTLDG Impedance */
#define TAS675X_CH1_RTLDG_IMP_MSB_REG 0xD1
#define TAS675X_CH1_RTLDG_IMP_LSB_REG 0xD2
#define TAS675X_CH2_RTLDG_IMP_MSB_REG 0xD3
#define TAS675X_CH2_RTLDG_IMP_LSB_REG 0xD4
#define TAS675X_CH3_RTLDG_IMP_MSB_REG 0xD5
#define TAS675X_CH3_RTLDG_IMP_LSB_REG 0xD6
#define TAS675X_CH4_RTLDG_IMP_MSB_REG 0xD7
#define TAS675X_CH4_RTLDG_IMP_LSB_REG 0xD8
/* DC Load Diagnostic Resistance */
#define TAS675X_DC_LDG_DCR_MSB_REG 0xD9
#define TAS675X_CH1_DC_LDG_DCR_LSB_REG 0xDA
#define TAS675X_CH2_DC_LDG_DCR_LSB_REG 0xDB
#define TAS675X_CH3_DC_LDG_DCR_LSB_REG 0xDC
#define TAS675X_CH4_DC_LDG_DCR_LSB_REG 0xDD
/* Over-Temperature Warning */
#define TAS675X_OTW_CTRL_CH1_CH2_REG 0xE2
#define TAS675X_OTW_CTRL_CH3_CH4_REG 0xE3
/* RESET_REG (all bits auto-clear) */
#define TAS675X_DEVICE_RESET BIT(4)
#define TAS675X_FAULT_CLEAR BIT(3)
#define TAS675X_REGISTER_RESET BIT(0)
/* STATE_CTRL and STATE_REPORT — Channel state values */
#define TAS675X_STATE_DEEPSLEEP 0x00
#define TAS675X_STATE_LOAD_DIAG 0x01
#define TAS675X_STATE_SLEEP 0x02
#define TAS675X_STATE_HIZ 0x03
#define TAS675X_STATE_PLAY 0x04
/* Additional STATE_REPORT values */
#define TAS675X_STATE_FAULT 0x05
#define TAS675X_STATE_AUTOREC 0x06
/* Combined values for both channel pairs in one register */
#define TAS675X_STATE_DEEPSLEEP_BOTH \
(TAS675X_STATE_DEEPSLEEP | (TAS675X_STATE_DEEPSLEEP << 4))
#define TAS675X_STATE_LOAD_DIAG_BOTH \
(TAS675X_STATE_LOAD_DIAG | (TAS675X_STATE_LOAD_DIAG << 4))
#define TAS675X_STATE_SLEEP_BOTH \
(TAS675X_STATE_SLEEP | (TAS675X_STATE_SLEEP << 4))
#define TAS675X_STATE_HIZ_BOTH \
(TAS675X_STATE_HIZ | (TAS675X_STATE_HIZ << 4))
#define TAS675X_STATE_PLAY_BOTH \
(TAS675X_STATE_PLAY | (TAS675X_STATE_PLAY << 4))
#define TAS675X_STATE_FAULT_BOTH \
(TAS675X_STATE_FAULT | (TAS675X_STATE_FAULT << 4))
/* STATE_CTRL_CH1_CH2 / STATE_CTRL_CH3_CH4 — mute bits */
#define TAS675X_CH1_MUTE_BIT BIT(7)
#define TAS675X_CH2_MUTE_BIT BIT(3)
#define TAS675X_CH_MUTE_BOTH (TAS675X_CH1_MUTE_BIT | TAS675X_CH2_MUTE_BIT)
/* SCLK_INV_CTRL_REG */
#define TAS675X_SCLK_INV_TX_BIT BIT(5)
#define TAS675X_SCLK_INV_RX_BIT BIT(4)
#define TAS675X_SCLK_INV_MASK (TAS675X_SCLK_INV_TX_BIT | TAS675X_SCLK_INV_RX_BIT)
/* AUDIO_IF_CTRL_REG */
#define TAS675X_TDM_EN_BIT BIT(4)
#define TAS675X_SAP_FMT_MASK GENMASK(3, 2)
#define TAS675X_SAP_FMT_I2S (0x00 << 2)
#define TAS675X_SAP_FMT_TDM (0x01 << 2)
#define TAS675X_SAP_FMT_RIGHT_J (0x02 << 2)
#define TAS675X_SAP_FMT_LEFT_J (0x03 << 2)
#define TAS675X_FS_PULSE_MASK GENMASK(1, 0)
#define TAS675X_FS_PULSE_SHORT 0x01
/* SDIN_CTRL_REG */
#define TAS675X_SDIN_AUDIO_WL_MASK GENMASK(3, 2)
#define TAS675X_SDIN_LL_WL_MASK GENMASK(1, 0)
#define TAS675X_SDIN_WL_MASK (TAS675X_SDIN_AUDIO_WL_MASK | TAS675X_SDIN_LL_WL_MASK)
/* SDOUT_CTRL_REG */
#define TAS675X_SDOUT_SELECT_MASK GENMASK(7, 4)
#define TAS675X_SDOUT_SELECT_TDM_SDOUT1 0x00
#define TAS675X_SDOUT_SELECT_NON_TDM 0x10
#define TAS675X_SDOUT_VP_WL_MASK GENMASK(3, 2)
#define TAS675X_SDOUT_IS_WL_MASK GENMASK(1, 0)
#define TAS675X_SDOUT_WL_MASK (TAS675X_SDOUT_VP_WL_MASK | TAS675X_SDOUT_IS_WL_MASK)
/* SDOUT_EN_REG */
#define TAS675X_SDOUT_NON_TDM_SEL_MASK GENMASK(5, 4)
#define TAS675X_SDOUT_NON_TDM_SEL_VPREDICT (0x0 << 4)
#define TAS675X_SDOUT_NON_TDM_SEL_ISENSE (0x1 << 4)
#define TAS675X_SDOUT_EN_VPREDICT BIT(0)
#define TAS675X_SDOUT_EN_ISENSE BIT(1)
#define TAS675X_SDOUT_EN_NON_TDM_ALL GENMASK(1, 0)
/* Word length values (shared by SDIN_CTRL and SDOUT_CTRL) */
#define TAS675X_WL_16BIT 0x00
#define TAS675X_WL_20BIT 0x01
#define TAS675X_WL_24BIT 0x02
#define TAS675X_WL_32BIT 0x03
/* SDIN_OFFSET_MSB_REG */
#define TAS675X_SDIN_AUDIO_OFF_MSB_MASK GENMASK(7, 6)
#define TAS675X_SDIN_LL_OFF_MSB_MASK GENMASK(5, 4)
/* SDOUT_OFFSET_MSB_REG */
#define TAS675X_SDOUT_VP_OFF_MSB_MASK GENMASK(7, 6)
#define TAS675X_SDOUT_IS_OFF_MSB_MASK GENMASK(5, 4)
/* RTLDG_EN_REG */
#define TAS675X_RTLDG_CLIP_MASK_BIT BIT(4)
#define TAS675X_RTLDG_CH_EN_MASK GENMASK(3, 0)
/* DC_LDG_CTRL_REG */
#define TAS675X_LDG_ABORT_BIT BIT(7)
#define TAS675X_LDG_BUFFER_WAIT_MASK GENMASK(6, 5)
#define TAS675X_LDG_WAIT_BYPASS_BIT BIT(2)
#define TAS675X_SLOL_DISABLE_BIT BIT(1)
#define TAS675X_LDG_BYPASS_BIT BIT(0)
/* DC_LDG_TIME_CTRL_REG */
#define TAS675X_LDG_RAMP_SLOL_MASK GENMASK(7, 6)
#define TAS675X_LDG_SETTLING_SLOL_MASK GENMASK(5, 4)
#define TAS675X_LDG_RAMP_S2PG_MASK GENMASK(3, 2)
#define TAS675X_LDG_SETTLING_S2PG_MASK GENMASK(1, 0)
/* AC_LDG_CTRL_REG */
#define TAS675X_AC_DIAG_GAIN_BIT BIT(4)
#define TAS675X_AC_DIAG_START_MASK GENMASK(3, 0)
/* DC_LDG_RESULT_REG */
#define TAS675X_DC_LDG_LO_RESULT_MASK GENMASK(7, 4)
#define TAS675X_DC_LDG_PASS_MASK GENMASK(3, 0)
/* Load Diagnostics Timing Constants */
#define TAS675X_POLL_INTERVAL_US 10000
#define TAS675X_STATE_TRANSITION_TIMEOUT_US 50000
#define TAS675X_DC_LDG_TIMEOUT_US 300000
#define TAS675X_AC_LDG_TIMEOUT_US 400000
/* GPIO_CTRL_REG */
#define TAS675X_GPIO1_OUTPUT_EN BIT(7)
#define TAS675X_GPIO2_OUTPUT_EN BIT(6)
#define TAS675X_GPIO_CTRL_RSTVAL 0x22
/* GPIO output select values */
#define TAS675X_GPIO_SEL_LOW 0x00
#define TAS675X_GPIO_SEL_AUTO_MUTE_ALL 0x02
#define TAS675X_GPIO_SEL_AUTO_MUTE_CH4 0x03
#define TAS675X_GPIO_SEL_AUTO_MUTE_CH3 0x04
#define TAS675X_GPIO_SEL_AUTO_MUTE_CH2 0x05
#define TAS675X_GPIO_SEL_AUTO_MUTE_CH1 0x06
#define TAS675X_GPIO_SEL_SDOUT2 0x08
#define TAS675X_GPIO_SEL_SDOUT1 0x09
#define TAS675X_GPIO_SEL_WARN 0x0A
#define TAS675X_GPIO_SEL_FAULT 0x0B
#define TAS675X_GPIO_SEL_CLOCK_SYNC 0x0E
#define TAS675X_GPIO_SEL_INVALID_CLK 0x0F
#define TAS675X_GPIO_SEL_HIGH 0x13
/* GPIO input function encoding (flag bit | function ID) */
#define TAS675X_GPIO_FUNC_INPUT 0x100
/* Input Function IDs */
#define TAS675X_GPIO_IN_ID_MUTE 0
#define TAS675X_GPIO_IN_ID_PHASE_SYNC 1
#define TAS675X_GPIO_IN_ID_SDIN2 2
#define TAS675X_GPIO_IN_ID_DEEP_SLEEP 3
#define TAS675X_GPIO_IN_ID_HIZ 4
#define TAS675X_GPIO_IN_ID_PLAY 5
#define TAS675X_GPIO_IN_ID_SLEEP 6
#define TAS675X_GPIO_IN_NUM 7
#define TAS675X_GPIO_IN_MUTE (TAS675X_GPIO_FUNC_INPUT | TAS675X_GPIO_IN_ID_MUTE)
#define TAS675X_GPIO_IN_PHASE_SYNC \
(TAS675X_GPIO_FUNC_INPUT | TAS675X_GPIO_IN_ID_PHASE_SYNC)
#define TAS675X_GPIO_IN_SDIN2 (TAS675X_GPIO_FUNC_INPUT | TAS675X_GPIO_IN_ID_SDIN2)
#define TAS675X_GPIO_IN_DEEP_SLEEP \
(TAS675X_GPIO_FUNC_INPUT | TAS675X_GPIO_IN_ID_DEEP_SLEEP)
#define TAS675X_GPIO_IN_HIZ (TAS675X_GPIO_FUNC_INPUT | TAS675X_GPIO_IN_ID_HIZ)
#define TAS675X_GPIO_IN_PLAY (TAS675X_GPIO_FUNC_INPUT | TAS675X_GPIO_IN_ID_PLAY)
#define TAS675X_GPIO_IN_SLEEP (TAS675X_GPIO_FUNC_INPUT | TAS675X_GPIO_IN_ID_SLEEP)
/* GPIO input 3-bit mux field masks */
#define TAS675X_GPIO_IN_MUTE_MASK GENMASK(2, 0)
#define TAS675X_GPIO_IN_SYNC_MASK GENMASK(2, 0)
#define TAS675X_GPIO_IN_SDIN2_MASK GENMASK(6, 4)
#define TAS675X_GPIO_IN_DEEP_SLEEP_MASK GENMASK(6, 4)
#define TAS675X_GPIO_IN_HIZ_MASK GENMASK(2, 0)
#define TAS675X_GPIO_IN_PLAY_MASK GENMASK(6, 4)
#define TAS675X_GPIO_IN_SLEEP_MASK GENMASK(2, 0)
/* Book addresses for tas675x_select_book() */
#define TAS675X_BOOK_DEFAULT 0x00
#define TAS675X_BOOK_DSP 0x8C
/* DSP memory addresses (DSP Book) */
#define TAS675X_DSP_PAGE_RTLDG 0x22
#define TAS675X_DSP_RTLDG_OL_THRESH_REG 0x98
#define TAS675X_DSP_RTLDG_SL_THRESH_REG 0x9C
#define TAS675X_DSP_PARAM_ID_OL_THRESH 0
#define TAS675X_DSP_PARAM_ID_SL_THRESH 1
/* Setup Mode Entry/Exit*/
#define TAS675X_SETUP_ENTER_VAL1 0x11
#define TAS675X_SETUP_ENTER_VAL2 0xFF
#define TAS675X_SETUP_EXIT_VAL 0x00
#endif /* __TAS675X_H__ */