mirrors/linux
2
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git synced 2026-06-10 18:13:28 -04:00
Code Issues Packages Projects Releases Wiki Activity

arm64: dts: imx8mp: Bind bluetooth UART on DH electronics i.MX8M Plus DHCOM

Browse Source 
The i.MX8MP DHCOM SoM does contain muRata 2AE WiFi+BT chip, bind the
bluetooth to UART2 using btbcm and hci_bcm drivers. Use PLL3 to drive
UART2 clock divided down to 64 MHz to obtain suitable block clock for
exact 4 Mbdps, which is the maximum supported baud rate by the muRata
2AE BT UART.

Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit is contained in:
Marek Vasut
2022-10-31 21:49:55 +01:00
committed by Shawn Guo
parent 3cad403f58
commit a9404a8917
1 changed files with 25 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

31
arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi
View File

@@ -427,6 +427,24 @@ &uart2 {
pinctrl-0 = <&pinctrl_uart2>;
uart-has-rtscts;
status = "okay";
/*
* PLL3 at 320 MHz supplies UART2 root with 64 MHz clock,
* which with 16x oversampling yields 4 Mbdps baud base,
* which is exactly the maximum rate supported by muRata
* 2AE bluetooth UART.
*/
assigned-clocks = <&clk IMX8MP_SYS_PLL3>, <&clk IMX8MP_CLK_UART2>;
assigned-clock-parents = <0>, <&clk IMX8MP_SYS_PLL3_OUT>;
assigned-clock-rates = <320000000>, <64000000>;
bluetooth {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2_bt>;
compatible = "cypress,cyw4373a0-bt";
shutdown-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
max-speed = <4000000>;
};
};
&uart3 {
@@ -849,6 +867,13 @@ MX8MP_IOMUXC_SD1_DATA5__UART2_DCE_CTS 0x49
>;
};
pinctrl_uart2_bt: dhcom-uart2-bt-grp {
fsl,pins = <
/* BT_REG_EN */
MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x144
>;
};
pinctrl_uart3: dhcom-uart3-grp {
fsl,pins = <
MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x49
@@ -886,8 +911,6 @@ MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0
/* BT_REG_EN */
MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x144
/* WL_REG_EN */
MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x144
>;
@@ -901,8 +924,6 @@ MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4
/* BT_REG_EN */
MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x144
/* WL_REG_EN */
MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x144
>;
@@ -916,8 +937,6 @@ MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6
MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6
MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6
MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6
/* BT_REG_EN */
MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x144
/* WL_REG_EN */
MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x144
>;