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drm/etnaviv: Add command stream definitions required for a PPU flop reset

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v2: move some defines that resided in etnaviv_flop_reset.c
    into the header as well

v3: fix spacing/tab stops

[cgmeiner: remove use of multiple blank lines]

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Tested-by: Marek Vasut <marek.vasut@mailbox.org> # STM32MP255C DHCOS DHSBC
Link: https://patch.msgid.link/20251119164624.9297-2-gert.wollny@collabora.com
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
This commit is contained in:
Gert Wollny
2025-11-19 17:45:47 +01:00
committed by Christian Gmeiner
parent 349d4efadc
commit a8fffbe7de
1 changed files with 95 additions and 0 deletions
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95
drivers/gpu/drm/etnaviv/state_3d.xml.h
View File

@@ -4,6 +4,101 @@
/* This is a cut-down version of the state_3d.xml.h file */
#define VIVS_CL_CONFIG 0x00000900
#define VIVS_CL_CONFIG_DIMENSIONS__MASK 0x00000003
#define VIVS_CL_CONFIG_DIMENSIONS__SHIFT 0
#define VIVS_CL_CONFIG_DIMENSIONS(x) (((x) << VIVS_CL_CONFIG_DIMENSIONS__SHIFT) & VIVS_CL_CONFIG_DIMENSIONS__MASK)
#define VIVS_CL_CONFIG_TRAVERSE_ORDER__MASK 0x00000070
#define VIVS_CL_CONFIG_TRAVERSE_ORDER__SHIFT 4
#define VIVS_CL_CONFIG_TRAVERSE_ORDER(x) (((x) << VIVS_CL_CONFIG_TRAVERSE_ORDER__SHIFT) & VIVS_CL_CONFIG_TRAVERSE_ORDER__MASK)
#define VIVS_CL_CONFIG_ENABLE_SWATH_X 0x00000100
#define VIVS_CL_CONFIG_ENABLE_SWATH_Y 0x00000200
#define VIVS_CL_CONFIG_ENABLE_SWATH_Z 0x00000400
#define VIVS_CL_CONFIG_SWATH_SIZE_X__MASK 0x0000f000
#define VIVS_CL_CONFIG_SWATH_SIZE_X__SHIFT 12
#define VIVS_CL_CONFIG_SWATH_SIZE_X(x) (((x) << VIVS_CL_CONFIG_SWATH_SIZE_X__SHIFT) & VIVS_CL_CONFIG_SWATH_SIZE_X__MASK)
#define VIVS_CL_CONFIG_SWATH_SIZE_Y__MASK 0x000f0000
#define VIVS_CL_CONFIG_SWATH_SIZE_Y__SHIFT 16
#define VIVS_CL_CONFIG_SWATH_SIZE_Y(x) (((x) << VIVS_CL_CONFIG_SWATH_SIZE_Y__SHIFT) & VIVS_CL_CONFIG_SWATH_SIZE_Y__MASK)
#define VIVS_CL_CONFIG_SWATH_SIZE_Z__MASK 0x00f00000
#define VIVS_CL_CONFIG_SWATH_SIZE_Z__SHIFT 20
#define VIVS_CL_CONFIG_SWATH_SIZE_Z(x) (((x) << VIVS_CL_CONFIG_SWATH_SIZE_Z__SHIFT) & VIVS_CL_CONFIG_SWATH_SIZE_Z__MASK)
#define VIVS_CL_CONFIG_DIMENSIONS__MASK 0x00000003
#define VIVS_CL_CONFIG_DIMENSIONS__SHIFT 0
#define VIVS_CL_CONFIG_DIMENSIONS(x) (((x) << VIVS_CL_CONFIG_DIMENSIONS__SHIFT) & VIVS_CL_CONFIG_DIMENSIONS__MASK)
#define VIVS_CL_CONFIG_VALUE_ORDER__MASK 0x07000000
#define VIVS_CL_CONFIG_VALUE_ORDER__SHIFT 24
#define VIVS_CL_CONFIG_VALUE_ORDER(x) (((x) << VIVS_CL_CONFIG_VALUE_ORDER__SHIFT) & VIVS_CL_CONFIG_VALUE_ORDER__MASK)
#define VIVS_CL_GLOBAL_WORK_OFFSET_X 0x0000092c
#define VIVS_CL_GLOBAL_WORK_OFFSET_Y 0x00000934
#define VIVS_CL_GLOBAL_WORK_OFFSET_Z 0x0000093c
#define VIVS_CL_KICKER 0x00000920
#define VIVS_CL_THREAD_ALLOCATION 0x0000091c
#define VIVS_CL_UNK00924 0x00000924
#define VIVS_CL_WORKGROUP_COUNT_X 0x00000940
#define VIVS_CL_WORKGROUP_COUNT_Y 0x00000944
#define VIVS_CL_WORKGROUP_COUNT_Z 0x00000948
#define VIVS_CL_WORKGROUP_SIZE_X 0x0000094c
#define VIVS_CL_WORKGROUP_SIZE_Y 0x00000950
#define VIVS_CL_WORKGROUP_SIZE_Z 0x00000954
#define VIVS_CL_GLOBAL_SCALE_X 0x00000958
#define VIVS_CL_GLOBAL_SCALE_Y 0x0000095c
#define VIVS_CL_GLOBAL_SCALE_Z 0x00000960
#define VIVS_PA_VS_OUTPUT_COUNT 0x00000aa8
#define VIVS_PS_CONTROL_EXT 0x00001030
#define VIVS_PS_ICACHE_COUNT 0x00001094
#define VIVS_PS_ICACHE_PREFETCH 0x00001048
#define VIVS_PS_INPUT_COUNT 0x00001008
#define VIVS_PS_INPUT_COUNT_COUNT__MASK 0x0000001f
#define VIVS_PS_INPUT_COUNT_COUNT__SHIFT 0
#define VIVS_PS_INPUT_COUNT_COUNT(x) (((x) << VIVS_PS_INPUT_COUNT_COUNT__SHIFT) & VIVS_PS_INPUT_COUNT_COUNT__MASK)
#define VIVS_PS_NEWRANGE_LOW 0x0000087c
#define VIVS_PS_NEWRANGE_HIGH 0x00001090
#define VIVS_PS_SAMPLER_BASE 0x00001058
#define VIVS_PS_UNIFORM_BASE 0x00001024
#define VIVS_PS_INST_ADDR 0x00001028
#define VIVS_PS_TEMP_REGISTER_CONTROL 0x0000100c
#define VIVS_PS_TEMP_REGISTER_CONTROL_NUM_TEMPS__MASK 0x0000003f
#define VIVS_PS_TEMP_REGISTER_CONTROL_NUM_TEMPS__SHIFT 0
#define VIVS_PS_TEMP_REGISTER_CONTROL_NUM_TEMPS(x) (((x) << VIVS_PS_TEMP_REGISTER_CONTROL_NUM_TEMPS__SHIFT) & VIVS_PS_TEMP_REGISTER_CONTROL_NUM_TEMPS__MASK)
#define VIVS_PS_VARYING_NUM_COMPONENTS(i0) (0x00001080 + 0x4*(i0))
#define VIVS_PS_VARYING_NUM_COMPONENTS__ESIZE 0x00000004
#define VIVS_PS_VARYING_NUM_COMPONENTS__LEN 0x00000004
#define VIVS_SH_CONFIG 0x00015600
#define VIVS_SH_CONFIG_RTNE_ROUNDING 0x00000002
#define VIVS_SH_HALTI5_UNIFORMS(i0) (0x00036000 + 0x4*(i0))
#define VIVS_SH_HALTI5_UNIFORMS__ESIZE 0x00000004
#define VIVS_SH_HALTI5_UNIFORMS__LEN 0x00000800
#define VIVS_VS_HALTI5_UNK008A0 0x000008a0
#define VIVS_VS_HALTI5_UNK008A0_A__MASK 0x0000003f
#define VIVS_VS_HALTI5_UNK008A0_A__SHIFT 0
#define VIVS_VS_HALTI5_UNK008A0_A(x) (((x) << VIVS_VS_HALTI5_UNK008A0_A__SHIFT) & VIVS_VS_HALTI5_UNK008A0_A__MASK)
#define VIVS_VS_ICACHE_CONTROL 0x00000868
#define VIVS_VS_ICACHE_CONTROL_ENABLE 0x00000001
#define VIVS_VS_ICACHE_INVALIDATE 0x000008b0
#define VIVS_VS_OUTPUT_COUNT 0x00000804
#define VIVS_VS_OUTPUT_COUNT_COUNT__MASK 0x000000ff
#define VIVS_VS_OUTPUT_COUNT_COUNT__SHIFT 0
#define VIVS_VS_OUTPUT_COUNT_COUNT(x) (((x) << VIVS_VS_OUTPUT_COUNT_COUNT__SHIFT) & VIVS_VS_OUTPUT_COUNT_COUNT__MASK)
#define VIVS_TS_FLUSH_CACHE 0x00001650
#define VIVS_TS_FLUSH_CACHE_FLUSH 0x00000001