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rtw89: 8852c: process efuse of phycap
Read phycap data programmed in efuse, and store them into array. Signed-off-by: Ping-Ke Shih <pkshih@realtek.com> Signed-off-by: Kalle Valo <kvalo@kernel.org> Link: https://lore.kernel.org/r/20220307060457.56789-13-pkshih@realtek.com
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@@ -2666,18 +2666,22 @@ struct rtw89_cfo_tracking_info {
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/* 2GL, 2GH, 5GL1, 5GH1, 5GM1, 5GM2, 5GH1, 5GH2 */
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#define TSSI_TRIM_CH_GROUP_NUM 8
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#define TSSI_TRIM_CH_GROUP_NUM_6G 16
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#define TSSI_CCK_CH_GROUP_NUM 6
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#define TSSI_MCS_2G_CH_GROUP_NUM 5
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#define TSSI_MCS_5G_CH_GROUP_NUM 14
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#define TSSI_MCS_6G_CH_GROUP_NUM 32
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#define TSSI_MCS_CH_GROUP_NUM \
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(TSSI_MCS_2G_CH_GROUP_NUM + TSSI_MCS_5G_CH_GROUP_NUM)
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struct rtw89_tssi_info {
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u8 thermal[RF_PATH_MAX];
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s8 tssi_trim[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM];
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s8 tssi_trim_6g[RF_PATH_MAX][TSSI_TRIM_CH_GROUP_NUM_6G];
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s8 tssi_cck[RF_PATH_MAX][TSSI_CCK_CH_GROUP_NUM];
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s8 tssi_mcs[RF_PATH_MAX][TSSI_MCS_CH_GROUP_NUM];
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s8 tssi_6g_mcs[RF_PATH_MAX][TSSI_MCS_6G_CH_GROUP_NUM];
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s8 extra_ofst[RF_PATH_MAX];
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bool tssi_tracking_check[RF_PATH_MAX];
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u8 default_txagc_offset[RF_PATH_MAX];
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@@ -2,6 +2,7 @@
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/* Copyright(c) 2019-2022 Realtek Corporation
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*/
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#include "debug.h"
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#include "fw.h"
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#include "mac.h"
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#include "reg.h"
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@@ -220,7 +221,163 @@ static int rtw8852c_pwr_off_func(struct rtw89_dev *rtwdev)
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return 0;
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}
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static void rtw8852c_phycap_parsing_tssi(struct rtw89_dev *rtwdev, u8 *phycap_map)
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{
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struct rtw89_tssi_info *tssi = &rtwdev->tssi;
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static const u32 tssi_trim_addr[RF_PATH_NUM_8852C] = {0x5D6, 0x5AB};
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static const u32 tssi_trim_addr_6g[RF_PATH_NUM_8852C] = {0x5CE, 0x5A3};
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u32 addr = rtwdev->chip->phycap_addr;
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bool pg = false;
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u32 ofst;
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u8 i, j;
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for (i = 0; i < RF_PATH_NUM_8852C; i++) {
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for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++) {
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/* addrs are in decreasing order */
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ofst = tssi_trim_addr[i] - addr - j;
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tssi->tssi_trim[i][j] = phycap_map[ofst];
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if (phycap_map[ofst] != 0xff)
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pg = true;
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}
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for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM_6G; j++) {
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/* addrs are in decreasing order */
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ofst = tssi_trim_addr_6g[i] - addr - j;
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tssi->tssi_trim_6g[i][j] = phycap_map[ofst];
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if (phycap_map[ofst] != 0xff)
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pg = true;
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}
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}
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if (!pg) {
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memset(tssi->tssi_trim, 0, sizeof(tssi->tssi_trim));
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memset(tssi->tssi_trim_6g, 0, sizeof(tssi->tssi_trim_6g));
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rtw89_debug(rtwdev, RTW89_DBG_TSSI,
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"[TSSI][TRIM] no PG, set all trim info to 0\n");
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}
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for (i = 0; i < RF_PATH_NUM_8852C; i++)
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for (j = 0; j < TSSI_TRIM_CH_GROUP_NUM; j++)
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rtw89_debug(rtwdev, RTW89_DBG_TSSI,
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"[TSSI] path=%d idx=%d trim=0x%x addr=0x%x\n",
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i, j, tssi->tssi_trim[i][j],
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tssi_trim_addr[i] - j);
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}
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static void rtw8852c_phycap_parsing_thermal_trim(struct rtw89_dev *rtwdev,
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u8 *phycap_map)
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{
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struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
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static const u32 thm_trim_addr[RF_PATH_NUM_8852C] = {0x5DF, 0x5DC};
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u32 addr = rtwdev->chip->phycap_addr;
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u8 i;
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for (i = 0; i < RF_PATH_NUM_8852C; i++) {
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info->thermal_trim[i] = phycap_map[thm_trim_addr[i] - addr];
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rtw89_debug(rtwdev, RTW89_DBG_RFK,
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"[THERMAL][TRIM] path=%d thermal_trim=0x%x\n",
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i, info->thermal_trim[i]);
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if (info->thermal_trim[i] != 0xff)
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info->pg_thermal_trim = true;
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}
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}
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static void rtw8852c_thermal_trim(struct rtw89_dev *rtwdev)
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{
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#define __thm_setting(raw) \
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({ \
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u8 __v = (raw); \
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((__v & 0x1) << 3) | ((__v & 0x1f) >> 1); \
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})
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struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
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u8 i, val;
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if (!info->pg_thermal_trim) {
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rtw89_debug(rtwdev, RTW89_DBG_RFK,
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"[THERMAL][TRIM] no PG, do nothing\n");
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return;
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}
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for (i = 0; i < RF_PATH_NUM_8852C; i++) {
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val = __thm_setting(info->thermal_trim[i]);
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rtw89_write_rf(rtwdev, i, RR_TM2, RR_TM2_OFF, val);
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rtw89_debug(rtwdev, RTW89_DBG_RFK,
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"[THERMAL][TRIM] path=%d thermal_setting=0x%x\n",
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i, val);
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}
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#undef __thm_setting
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}
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static void rtw8852c_phycap_parsing_pa_bias_trim(struct rtw89_dev *rtwdev,
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u8 *phycap_map)
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{
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struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
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static const u32 pabias_trim_addr[RF_PATH_NUM_8852C] = {0x5DE, 0x5DB};
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u32 addr = rtwdev->chip->phycap_addr;
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u8 i;
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for (i = 0; i < RF_PATH_NUM_8852C; i++) {
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info->pa_bias_trim[i] = phycap_map[pabias_trim_addr[i] - addr];
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rtw89_debug(rtwdev, RTW89_DBG_RFK,
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"[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n",
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i, info->pa_bias_trim[i]);
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if (info->pa_bias_trim[i] != 0xff)
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info->pg_pa_bias_trim = true;
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}
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}
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static void rtw8852c_pa_bias_trim(struct rtw89_dev *rtwdev)
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{
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struct rtw89_power_trim_info *info = &rtwdev->pwr_trim;
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u8 pabias_2g, pabias_5g;
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u8 i;
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if (!info->pg_pa_bias_trim) {
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rtw89_debug(rtwdev, RTW89_DBG_RFK,
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"[PA_BIAS][TRIM] no PG, do nothing\n");
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return;
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}
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for (i = 0; i < RF_PATH_NUM_8852C; i++) {
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pabias_2g = FIELD_GET(GENMASK(3, 0), info->pa_bias_trim[i]);
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pabias_5g = FIELD_GET(GENMASK(7, 4), info->pa_bias_trim[i]);
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rtw89_debug(rtwdev, RTW89_DBG_RFK,
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"[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n",
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i, pabias_2g, pabias_5g);
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rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXG, pabias_2g);
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rtw89_write_rf(rtwdev, i, RR_BIASA, RR_BIASA_TXA, pabias_5g);
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}
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}
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static int rtw8852c_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map)
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{
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rtw8852c_phycap_parsing_tssi(rtwdev, phycap_map);
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rtw8852c_phycap_parsing_thermal_trim(rtwdev, phycap_map);
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rtw8852c_phycap_parsing_pa_bias_trim(rtwdev, phycap_map);
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return 0;
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}
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static void rtw8852c_power_trim(struct rtw89_dev *rtwdev)
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{
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rtw8852c_thermal_trim(rtwdev);
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rtw8852c_pa_bias_trim(rtwdev);
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}
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static const struct rtw89_chip_ops rtw8852c_chip_ops = {
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.read_phycap = rtw8852c_read_phycap,
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.power_trim = rtw8852c_power_trim,
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.pwr_on_func = rtw8852c_pwr_on_func,
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.pwr_off_func = rtw8852c_pwr_off_func,
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};
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@@ -238,6 +395,8 @@ const struct rtw89_chip_info rtw8852c_chip_info = {
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.limit_efuse_size = 1280,
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.dav_phy_efuse_size = 96,
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.dav_log_efuse_size = 16,
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.phycap_addr = 0x590,
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.phycap_size = 0x60,
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.hci_func_en_addr = R_AX_HCI_FUNC_EN_V1,
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.h2c_ctrl_reg = R_AX_H2CREG_CTRL_V1,
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.h2c_regs = rtw8852c_h2c_regs,
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@@ -7,6 +7,8 @@
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#include "core.h"
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#define RF_PATH_NUM_8852C 2
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extern const struct rtw89_chip_info rtw8852c_chip_info;
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#endif
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