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staging: wfx: add I/O API
hwio.c provides an abstraction to access different types of register of the chip. Note that only data register (aka FRAME_OUT) and control register are used normal communication. Other registers are only used during chip start up. Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com> Link: https://lore.kernel.org/r/20190919142527.31797-4-Jerome.Pouiller@silabs.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Jérôme Pouiller
committed by
Greg Kroah-Hartman
Greg Kroah-Hartman
parent
0096214a59
commit
a794e8b6fa
@@ -1,6 +1,7 @@
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# SPDX-License-Identifier: GPL-2.0
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wfx-y := \
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hwio.o \
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main.o
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wfx-$(CONFIG_SPI) += bus_spi.o
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wfx-$(subst m,y,$(CONFIG_MMC)) += bus_sdio.o
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327
drivers/staging/wfx/hwio.c
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327
drivers/staging/wfx/hwio.c
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@@ -0,0 +1,327 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Low-level I/O functions.
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*
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* Copyright (c) 2017-2019, Silicon Laboratories, Inc.
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* Copyright (c) 2010, ST-Ericsson
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*/
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#include <linux/kernel.h>
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#include <linux/delay.h>
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#include <linux/slab.h>
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#include "hwio.h"
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#include "wfx.h"
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#include "bus.h"
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/*
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* Internal helpers.
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*
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* About CONFIG_VMAP_STACK:
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* When CONFIG_VMAP_STACK is enabled, it is not possible to run DMA on stack
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* allocated data. Functions below that work with registers (aka functions
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* ending with "32") automatically reallocate buffers with kmalloc. However,
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* functions that work with arbitrary length buffers let's caller to handle
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* memory location. In doubt, enable CONFIG_DEBUG_SG to detect badly located
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* buffer.
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*/
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static int read32(struct wfx_dev *wdev, int reg, u32 *val)
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{
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int ret;
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__le32 *tmp = kmalloc(sizeof(u32), GFP_KERNEL);
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*val = ~0; // Never return undefined value
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if (!tmp)
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return -ENOMEM;
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ret = wdev->hwbus_ops->copy_from_io(wdev->hwbus_priv, reg, tmp, sizeof(u32));
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if (ret >= 0)
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*val = le32_to_cpu(*tmp);
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kfree(tmp);
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if (ret)
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dev_err(wdev->dev, "%s: bus communication error: %d\n", __func__, ret);
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return ret;
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}
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static int write32(struct wfx_dev *wdev, int reg, u32 val)
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{
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int ret;
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__le32 *tmp = kmalloc(sizeof(u32), GFP_KERNEL);
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if (!tmp)
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return -ENOMEM;
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*tmp = cpu_to_le32(val);
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ret = wdev->hwbus_ops->copy_to_io(wdev->hwbus_priv, reg, tmp, sizeof(u32));
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kfree(tmp);
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if (ret)
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dev_err(wdev->dev, "%s: bus communication error: %d\n", __func__, ret);
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return ret;
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}
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static int read32_locked(struct wfx_dev *wdev, int reg, u32 *val)
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{
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int ret;
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wdev->hwbus_ops->lock(wdev->hwbus_priv);
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ret = read32(wdev, reg, val);
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wdev->hwbus_ops->unlock(wdev->hwbus_priv);
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return ret;
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}
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static int write32_locked(struct wfx_dev *wdev, int reg, u32 val)
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{
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int ret;
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wdev->hwbus_ops->lock(wdev->hwbus_priv);
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ret = write32(wdev, reg, val);
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wdev->hwbus_ops->unlock(wdev->hwbus_priv);
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return ret;
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}
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static int write32_bits_locked(struct wfx_dev *wdev, int reg, u32 mask, u32 val)
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{
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int ret;
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u32 val_r, val_w;
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WARN_ON(~mask & val);
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val &= mask;
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wdev->hwbus_ops->lock(wdev->hwbus_priv);
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ret = read32(wdev, reg, &val_r);
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if (ret < 0)
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goto err;
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val_w = (val_r & ~mask) | val;
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if (val_w != val_r) {
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ret = write32(wdev, reg, val_w);
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}
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err:
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wdev->hwbus_ops->unlock(wdev->hwbus_priv);
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return ret;
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}
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static int indirect_read(struct wfx_dev *wdev, int reg, u32 addr, void *buf, size_t len)
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{
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int ret;
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int i;
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u32 cfg;
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u32 prefetch;
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WARN_ON(len >= 0x2000);
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WARN_ON(reg != WFX_REG_AHB_DPORT && reg != WFX_REG_SRAM_DPORT);
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if (reg == WFX_REG_AHB_DPORT)
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prefetch = CFG_PREFETCH_AHB;
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else if (reg == WFX_REG_SRAM_DPORT)
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prefetch = CFG_PREFETCH_SRAM;
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else
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return -ENODEV;
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ret = write32(wdev, WFX_REG_BASE_ADDR, addr);
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if (ret < 0)
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goto err;
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ret = read32(wdev, WFX_REG_CONFIG, &cfg);
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if (ret < 0)
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goto err;
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ret = write32(wdev, WFX_REG_CONFIG, cfg | prefetch);
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if (ret < 0)
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goto err;
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for (i = 0; i < 20; i++) {
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ret = read32(wdev, WFX_REG_CONFIG, &cfg);
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if (ret < 0)
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goto err;
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if (!(cfg & prefetch))
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break;
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udelay(200);
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}
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if (i == 20) {
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ret = -ETIMEDOUT;
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goto err;
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}
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ret = wdev->hwbus_ops->copy_from_io(wdev->hwbus_priv, reg, buf, len);
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err:
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if (ret < 0)
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memset(buf, 0xFF, len); // Never return undefined value
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return ret;
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}
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static int indirect_write(struct wfx_dev *wdev, int reg, u32 addr, const void *buf, size_t len)
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{
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int ret;
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WARN_ON(len >= 0x2000);
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WARN_ON(reg != WFX_REG_AHB_DPORT && reg != WFX_REG_SRAM_DPORT);
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ret = write32(wdev, WFX_REG_BASE_ADDR, addr);
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if (ret < 0)
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return ret;
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return wdev->hwbus_ops->copy_to_io(wdev->hwbus_priv, reg, buf, len);
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}
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static int indirect_read_locked(struct wfx_dev *wdev, int reg, u32 addr, void *buf, size_t len)
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{
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int ret;
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wdev->hwbus_ops->lock(wdev->hwbus_priv);
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ret = indirect_read(wdev, reg, addr, buf, len);
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wdev->hwbus_ops->unlock(wdev->hwbus_priv);
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return ret;
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}
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static int indirect_write_locked(struct wfx_dev *wdev, int reg, u32 addr, const void *buf, size_t len)
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{
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int ret;
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wdev->hwbus_ops->lock(wdev->hwbus_priv);
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ret = indirect_write(wdev, reg, addr, buf, len);
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wdev->hwbus_ops->unlock(wdev->hwbus_priv);
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return ret;
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}
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static int indirect_read32_locked(struct wfx_dev *wdev, int reg, u32 addr, u32 *val)
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{
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int ret;
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__le32 *tmp = kmalloc(sizeof(u32), GFP_KERNEL);
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if (!tmp)
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return -ENOMEM;
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wdev->hwbus_ops->lock(wdev->hwbus_priv);
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ret = indirect_read(wdev, reg, addr, tmp, sizeof(u32));
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*val = cpu_to_le32(*tmp);
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wdev->hwbus_ops->unlock(wdev->hwbus_priv);
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kfree(tmp);
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return ret;
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}
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static int indirect_write32_locked(struct wfx_dev *wdev, int reg, u32 addr, u32 val)
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{
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int ret;
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__le32 *tmp = kmalloc(sizeof(u32), GFP_KERNEL);
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if (!tmp)
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return -ENOMEM;
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*tmp = cpu_to_le32(val);
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wdev->hwbus_ops->lock(wdev->hwbus_priv);
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ret = indirect_write(wdev, reg, addr, tmp, sizeof(u32));
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wdev->hwbus_ops->unlock(wdev->hwbus_priv);
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kfree(tmp);
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return ret;
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}
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int wfx_data_read(struct wfx_dev *wdev, void *buf, size_t len)
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{
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int ret;
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WARN((long) buf & 3, "%s: unaligned buffer", __func__);
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wdev->hwbus_ops->lock(wdev->hwbus_priv);
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ret = wdev->hwbus_ops->copy_from_io(wdev->hwbus_priv, WFX_REG_IN_OUT_QUEUE, buf, len);
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wdev->hwbus_ops->unlock(wdev->hwbus_priv);
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if (ret)
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dev_err(wdev->dev, "%s: bus communication error: %d\n", __func__, ret);
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return ret;
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}
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int wfx_data_write(struct wfx_dev *wdev, const void *buf, size_t len)
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{
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int ret;
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WARN((long) buf & 3, "%s: unaligned buffer", __func__);
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wdev->hwbus_ops->lock(wdev->hwbus_priv);
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ret = wdev->hwbus_ops->copy_to_io(wdev->hwbus_priv, WFX_REG_IN_OUT_QUEUE, buf, len);
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wdev->hwbus_ops->unlock(wdev->hwbus_priv);
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if (ret)
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dev_err(wdev->dev, "%s: bus communication error: %d\n", __func__, ret);
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return ret;
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}
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int sram_buf_read(struct wfx_dev *wdev, u32 addr, void *buf, size_t len)
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{
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return indirect_read_locked(wdev, WFX_REG_SRAM_DPORT, addr, buf, len);
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}
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int ahb_buf_read(struct wfx_dev *wdev, u32 addr, void *buf, size_t len)
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{
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return indirect_read_locked(wdev, WFX_REG_AHB_DPORT, addr, buf, len);
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}
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int sram_buf_write(struct wfx_dev *wdev, u32 addr, const void *buf, size_t len)
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{
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return indirect_write_locked(wdev, WFX_REG_SRAM_DPORT, addr, buf, len);
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}
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int ahb_buf_write(struct wfx_dev *wdev, u32 addr, const void *buf, size_t len)
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{
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return indirect_write_locked(wdev, WFX_REG_AHB_DPORT, addr, buf, len);
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}
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int sram_reg_read(struct wfx_dev *wdev, u32 addr, u32 *val)
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{
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return indirect_read32_locked(wdev, WFX_REG_SRAM_DPORT, addr, val);
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}
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int ahb_reg_read(struct wfx_dev *wdev, u32 addr, u32 *val)
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{
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return indirect_read32_locked(wdev, WFX_REG_AHB_DPORT, addr, val);
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}
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int sram_reg_write(struct wfx_dev *wdev, u32 addr, u32 val)
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{
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return indirect_write32_locked(wdev, WFX_REG_SRAM_DPORT, addr, val);
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}
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int ahb_reg_write(struct wfx_dev *wdev, u32 addr, u32 val)
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{
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return indirect_write32_locked(wdev, WFX_REG_AHB_DPORT, addr, val);
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}
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int config_reg_read(struct wfx_dev *wdev, u32 *val)
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{
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return read32_locked(wdev, WFX_REG_CONFIG, val);
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}
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int config_reg_write(struct wfx_dev *wdev, u32 val)
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{
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return write32_locked(wdev, WFX_REG_CONFIG, val);
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}
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int config_reg_write_bits(struct wfx_dev *wdev, u32 mask, u32 val)
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{
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return write32_bits_locked(wdev, WFX_REG_CONFIG, mask, val);
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}
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int control_reg_read(struct wfx_dev *wdev, u32 *val)
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{
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return read32_locked(wdev, WFX_REG_CONTROL, val);
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}
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int control_reg_write(struct wfx_dev *wdev, u32 val)
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{
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return write32_locked(wdev, WFX_REG_CONTROL, val);
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}
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int control_reg_write_bits(struct wfx_dev *wdev, u32 mask, u32 val)
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{
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return write32_bits_locked(wdev, WFX_REG_CONTROL, mask, val);
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}
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int igpr_reg_read(struct wfx_dev *wdev, int index, u32 *val)
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{
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int ret;
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*val = ~0; // Never return undefined value
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ret = write32_locked(wdev, WFX_REG_SET_GEN_R_W, IGPR_RW | index << 24);
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if (ret)
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return ret;
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ret = read32_locked(wdev, WFX_REG_SET_GEN_R_W, val);
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if (ret)
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return ret;
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*val &= IGPR_VALUE;
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return ret;
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}
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int igpr_reg_write(struct wfx_dev *wdev, int index, u32 val)
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{
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return write32_locked(wdev, WFX_REG_SET_GEN_R_W, index << 24 | val);
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}
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@@ -8,6 +8,25 @@
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#ifndef WFX_HWIO_H
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#define WFX_HWIO_H
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#include <linux/types.h>
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struct wfx_dev;
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int wfx_data_read(struct wfx_dev *wdev, void *buf, size_t buf_len);
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int wfx_data_write(struct wfx_dev *wdev, const void *buf, size_t buf_len);
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int sram_buf_read(struct wfx_dev *wdev, u32 addr, void *buf, size_t len);
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int sram_buf_write(struct wfx_dev *wdev, u32 addr, const void *buf, size_t len);
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int ahb_buf_read(struct wfx_dev *wdev, u32 addr, void *buf, size_t len);
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int ahb_buf_write(struct wfx_dev *wdev, u32 addr, const void *buf, size_t len);
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int sram_reg_read(struct wfx_dev *wdev, u32 addr, u32 *val);
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int sram_reg_write(struct wfx_dev *wdev, u32 addr, u32 val);
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int ahb_reg_read(struct wfx_dev *wdev, u32 addr, u32 *val);
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int ahb_reg_write(struct wfx_dev *wdev, u32 addr, u32 val);
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#define CFG_ERR_SPI_FRAME 0x00000001 // only with SPI
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#define CFG_ERR_SDIO_BUF_MISMATCH 0x00000001 // only with SDIO
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#define CFG_ERR_BUF_UNDERRUN 0x00000002
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@@ -36,13 +55,21 @@
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#define CFG_DEVICE_ID_MAJOR 0x07000000
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#define CFG_DEVICE_ID_RESERVED 0x78000000
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#define CFG_DEVICE_ID_TYPE 0x80000000
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int config_reg_read(struct wfx_dev *wdev, u32 *val);
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int config_reg_write(struct wfx_dev *wdev, u32 val);
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int config_reg_write_bits(struct wfx_dev *wdev, u32 mask, u32 val);
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#define CTRL_NEXT_LEN_MASK 0x00000FFF
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#define CTRL_WLAN_WAKEUP 0x00001000
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#define CTRL_WLAN_READY 0x00002000
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int control_reg_read(struct wfx_dev *wdev, u32 *val);
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int control_reg_write(struct wfx_dev *wdev, u32 val);
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int control_reg_write_bits(struct wfx_dev *wdev, u32 mask, u32 val);
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#define IGPR_RW 0x80000000
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#define IGPR_INDEX 0x7F000000
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#define IGPR_VALUE 0x00FFFFFF
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int igpr_reg_read(struct wfx_dev *wdev, int index, u32 *val);
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int igpr_reg_write(struct wfx_dev *wdev, int index, u32 val);
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#endif /* WFX_HWIO_H */
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