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drm/i915/bxt: Clean up bxt_init_clock_gating

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Add stepping check for A0 workarounds, and remove the associated
FIXME tags.
Split out unrelated WAs for later condition checking.

v2: Fixed format (PeterL)
v3: Corrected stepping check for WaDisableSDEUnitClockGating
    - Ignoring comment, following hardware spec instead. (ChrisH)
    Added description for TILECTL setting (JonB)

Cc: Peter Lawthers <peter.lawthers@intel.com>
Cc: Chris Harris <chris.harris@intel.com>
Cc: Jon Bloomfield <jon.bloomfield@intel.com>
Signed-off-by: Nick Hoath <nicholas.hoath@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
Nick Hoath
2015-06-29 14:07:32 +01:00
committed by Daniel Vetter
parent 614f4ad798
commit a754615971
1 changed files with 11 additions and 5 deletions
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16
drivers/gpu/drm/i915/intel_pm.c
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@@ -116,18 +116,24 @@ static void bxt_init_clock_gating(struct drm_device *dev)
gen9_init_clock_gating(dev);
/* WaDisableSDEUnitClockGating:bxt */
I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
/*
* FIXME:
* GEN8_SDEUNIT_CLOCK_GATE_DISABLE applies on A0 only.
* GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
*/
/* WaDisableSDEUnitClockGating:bxt */
I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
GEN8_SDEUNIT_CLOCK_GATE_DISABLE |
GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
/* FIXME: apply on A0 only */
I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
if (INTEL_REVID(dev) == BXT_REVID_A0) {
/*
* Hardware specification requires this bit to be
* set to 1 for A0
*/
I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
}
}
static void i915_pineview_get_mem_freq(struct drm_device *dev)