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Merge tag 'hisi-arm32-dt-for-5.10' of git://github.com/hisilicon/linux-hisi into arm/dt

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ARM: DT: Hisilicon ARM32 SoCs DT updates for 5.10

- Update the SP804 nodes to have the correct clocks and
  clock names for the hi3620 SoC
- Update the SP805 nodes to have the correct clocks and
  clock names for the hix5hd2 SoC

* tag 'hisi-arm32-dt-for-5.10' of git://github.com/hisilicon/linux-hisi:
  ARM: dts: hisilicon: Fix SP805 clocks
  ARM: dts: hisilicon: Fix SP804 users

Link: https://lore.kernel.org/r/5F617209.90003@hisilicon.com
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
2020-09-26 09:46:29 -07:00
parent 39d601ba9a 3328c65666
commit a7140476d6
3 changed files with 25 additions and 14 deletions
Download Patch File Download Diff File Expand all files Collapse all files

30
arch/arm/boot/dts/hi3620.dtsi
View File

@@ -111,8 +111,10 @@ dual_timer0: dual_timer@800000 {
reg = <0x800000 0x1000>;
/* timer00 & timer01 */
interrupts = <0 0 4>, <0 1 4>;
clocks = <&clock HI3620_TIMER0_MUX>, <&clock HI3620_TIMER1_MUX>;
clock-names = "apb_pclk";
clocks = <&clock HI3620_TIMER0_MUX>,
<&clock HI3620_TIMER1_MUX>,
<&clock HI3620_TIMER0_MUX>;
clock-names = "timer0clk", "timer1clk", "apb_pclk";
status = "disabled";
};
@@ -121,8 +123,10 @@ dual_timer1: dual_timer@801000 {
reg = <0x801000 0x1000>;
/* timer10 & timer11 */
interrupts = <0 2 4>, <0 3 4>;
clocks = <&clock HI3620_TIMER2_MUX>, <&clock HI3620_TIMER3_MUX>;
clock-names = "apb_pclk";
clocks = <&clock HI3620_TIMER2_MUX>,
<&clock HI3620_TIMER3_MUX>,
<&clock HI3620_TIMER2_MUX>;
clock-names = "timer0clk", "timer1clk", "apb_pclk";
status = "disabled";
};
@@ -131,8 +135,10 @@ dual_timer2: dual_timer@a01000 {
reg = <0xa01000 0x1000>;
/* timer20 & timer21 */
interrupts = <0 4 4>, <0 5 4>;
clocks = <&clock HI3620_TIMER4_MUX>, <&clock HI3620_TIMER5_MUX>;
clock-names = "apb_pclk";
clocks = <&clock HI3620_TIMER4_MUX>,
<&clock HI3620_TIMER5_MUX>,
<&clock HI3620_TIMER4_MUX>;
clock-names = "timer0lck", "timer1clk", "apb_pclk";
status = "disabled";
};
@@ -141,8 +147,10 @@ dual_timer3: dual_timer@a02000 {
reg = <0xa02000 0x1000>;
/* timer30 & timer31 */
interrupts = <0 6 4>, <0 7 4>;
clocks = <&clock HI3620_TIMER6_MUX>, <&clock HI3620_TIMER7_MUX>;
clock-names = "apb_pclk";
clocks = <&clock HI3620_TIMER6_MUX>,
<&clock HI3620_TIMER7_MUX>,
<&clock HI3620_TIMER6_MUX>;
clock-names = "timer0clk", "timer1clk", "apb_pclk";
status = "disabled";
};
@@ -151,8 +159,10 @@ dual_timer4: dual_timer@a03000 {
reg = <0xa03000 0x1000>;
/* timer40 & timer41 */
interrupts = <0 96 4>, <0 97 4>;
clocks = <&clock HI3620_TIMER8_MUX>, <&clock HI3620_TIMER9_MUX>;
clock-names = "apb_pclk";
clocks = <&clock HI3620_TIMER8_MUX>,
<&clock HI3620_TIMER9_MUX>,
<&clock HI3620_TIMER8_MUX>;
clock-names = "timer0clk", "timer1clk", "apb_pclk";
status = "disabled";
};

4
arch/arm/boot/dts/hip04.dtsi
View File

@@ -226,8 +226,8 @@ dual_timer0: dual_timer@3000000 {
compatible = "arm,sp804", "arm,primecell";
reg = <0x3000000 0x1000>;
interrupts = <0 224 4>;
clocks = <&clk_50m>, <&clk_50m>;
clock-names = "apb_pclk";
clocks = <&clk_50m>, <&clk_50m>, <&clk_50m>;
clock-names = "timer0clk", "timer1clk", "apb_pclk";
};
arm-pmu {

5
arch/arm/boot/dts/hisi-x5hd2.dtsi
View File

@@ -370,8 +370,9 @@ wdt0: watchdog@a2c000 {
arm,primecell-periphid = <0x00141805>;
reg = <0xa2c000 0x1000>;
interrupts = <0 29 4>;
clocks = <&clock HIX5HD2_WDG0_RST>;
clock-names = "apb_pclk";
clocks = <&clock HIX5HD2_WDG0_RST>,
<&clock HIX5HD2_WDG0_RST>;
clock-names = "wdog_clk", "apb_pclk";
};
};