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staging: rtl8188eu: simplify phy_iq_calibrate
phy_iq_calibrate's is2t parameter is always false. Remove some code that would be called only for is2t == true. Signed-off-by: Martin Kaiser <martin@kaiser.cx> Link: https://lore.kernel.org/r/20210725155902.32433-15-martin@kaiser.cx Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
committed by
Greg Kroah-Hartman
parent
e17c7d42cd
commit
a70a91b01d
@@ -625,38 +625,6 @@ static u8 phy_path_a_rx_iqk(struct adapter *adapt, bool configPathB)
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return result;
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}
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static u8 phy_path_b_iqk(struct adapter *adapt)
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{
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u32 regeac, regeb4, regebc, regec4, regecc;
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u8 result = 0x00;
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/* One shot, path B LOK & IQK */
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phy_set_bb_reg(adapt, rIQK_AGC_Cont, bMaskDWord, 0x00000002);
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phy_set_bb_reg(adapt, rIQK_AGC_Cont, bMaskDWord, 0x00000000);
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mdelay(IQK_DELAY_TIME_88E);
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regeac = phy_query_bb_reg(adapt, rRx_Power_After_IQK_A_2, bMaskDWord);
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regeb4 = phy_query_bb_reg(adapt, rTx_Power_Before_IQK_B, bMaskDWord);
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regebc = phy_query_bb_reg(adapt, rTx_Power_After_IQK_B, bMaskDWord);
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regec4 = phy_query_bb_reg(adapt, rRx_Power_Before_IQK_B_2, bMaskDWord);
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regecc = phy_query_bb_reg(adapt, rRx_Power_After_IQK_B_2, bMaskDWord);
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if (!(regeac & BIT(31)) &&
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(((regeb4 & 0x03FF0000) >> 16) != 0x142) &&
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(((regebc & 0x03FF0000) >> 16) != 0x42))
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result |= 0x01;
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else
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return result;
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if (!(regeac & BIT(30)) &&
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(((regec4 & 0x03FF0000) >> 16) != 0x132) &&
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(((regecc & 0x03FF0000) >> 16) != 0x36))
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result |= 0x02;
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return result;
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}
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static void patha_fill_iqk(struct adapter *adapt, bool iqkok, s32 result[][8],
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u8 final_candidate, bool txonly)
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{
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@@ -774,13 +742,6 @@ static void mac_setting_calibration(struct adapter *adapt, const u32 *mac_reg,
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usb_write8(adapt, mac_reg[i], (u8)(backup[i] & (~BIT(5))));
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}
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static void path_a_standby(struct adapter *adapt)
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{
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phy_set_bb_reg(adapt, rFPGA0_IQK, bMaskDWord, 0x0);
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phy_set_bb_reg(adapt, 0x840, bMaskDWord, 0x00010000);
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phy_set_bb_reg(adapt, rFPGA0_IQK, bMaskDWord, 0x80800000);
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}
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static void pi_mode_switch(struct adapter *adapt, bool pi_mode)
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{
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u32 mode;
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@@ -865,11 +826,11 @@ static bool simularity_compare(struct adapter *adapt, s32 resulta[][8],
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}
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static void phy_iq_calibrate(struct adapter *adapt, s32 result[][8],
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u8 t, bool is2t)
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u8 t)
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{
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struct odm_dm_struct *dm_odm = &adapt->HalData->odmpriv;
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u32 i;
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u8 path_a_ok, path_b_ok;
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u8 path_a_ok;
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static const u32 adda_reg[IQK_ADDA_REG_NUM] = {
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rFPGA0_XCD_SwitchControl, rBlue_Tooth,
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rRx_Wait_CCA, rTx_CCK_RFON,
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@@ -909,7 +870,7 @@ static void phy_iq_calibrate(struct adapter *adapt, s32 result[][8],
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dm_odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM);
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}
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path_adda_on(adapt, adda_reg, true, is2t);
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path_adda_on(adapt, adda_reg, true, false);
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if (t == 0)
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dm_odm->RFCalibrateInfo.bRfPiEnable = (u8)phy_query_bb_reg(adapt, rFPGA0_XA_HSSIParameter1,
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BIT(8));
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@@ -930,13 +891,6 @@ static void phy_iq_calibrate(struct adapter *adapt, s32 result[][8],
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phy_set_bb_reg(adapt, rFPGA0_XA_RFInterfaceOE, BIT(10), 0x00);
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phy_set_bb_reg(adapt, rFPGA0_XB_RFInterfaceOE, BIT(10), 0x00);
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if (is2t) {
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phy_set_bb_reg(adapt, rFPGA0_XA_LSSIParameter, bMaskDWord,
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0x00010000);
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phy_set_bb_reg(adapt, rFPGA0_XB_LSSIParameter, bMaskDWord,
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0x00010000);
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}
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/* MAC settings */
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mac_setting_calibration(adapt, iqk_mac_reg,
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dm_odm->RFCalibrateInfo.IQK_MAC_backup);
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@@ -945,16 +899,13 @@ static void phy_iq_calibrate(struct adapter *adapt, s32 result[][8],
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/* AP or IQK */
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phy_set_bb_reg(adapt, rConfig_AntA, bMaskDWord, 0x0f600000);
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if (is2t)
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phy_set_bb_reg(adapt, rConfig_AntB, bMaskDWord, 0x0f600000);
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/* IQ calibration setting */
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phy_set_bb_reg(adapt, rFPGA0_IQK, bMaskDWord, 0x80800000);
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phy_set_bb_reg(adapt, rTx_IQK, bMaskDWord, 0x01007c00);
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phy_set_bb_reg(adapt, rRx_IQK, bMaskDWord, 0x81004800);
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for (i = 0; i < retry_count; i++) {
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path_a_ok = phy_path_a_iqk(adapt, is2t);
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path_a_ok = phy_path_a_iqk(adapt, false);
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if (path_a_ok == 0x01) {
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result[t][0] = (phy_query_bb_reg(adapt, rTx_Power_Before_IQK_A,
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bMaskDWord) & 0x3FF0000) >> 16;
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@@ -965,7 +916,7 @@ static void phy_iq_calibrate(struct adapter *adapt, s32 result[][8],
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}
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for (i = 0; i < retry_count; i++) {
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path_a_ok = phy_path_a_rx_iqk(adapt, is2t);
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path_a_ok = phy_path_a_rx_iqk(adapt, false);
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if (path_a_ok == 0x03) {
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result[t][2] = (phy_query_bb_reg(adapt, rRx_Power_Before_IQK_A_2,
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bMaskDWord) & 0x3FF0000) >> 16;
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@@ -975,33 +926,6 @@ static void phy_iq_calibrate(struct adapter *adapt, s32 result[][8],
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}
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}
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if (is2t) {
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path_a_standby(adapt);
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/* Turn Path B ADDA on */
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path_adda_on(adapt, adda_reg, false, is2t);
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for (i = 0; i < retry_count; i++) {
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path_b_ok = phy_path_b_iqk(adapt);
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if (path_b_ok == 0x03) {
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result[t][4] = (phy_query_bb_reg(adapt, rTx_Power_Before_IQK_B,
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bMaskDWord) & 0x3FF0000) >> 16;
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result[t][5] = (phy_query_bb_reg(adapt, rTx_Power_After_IQK_B,
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bMaskDWord) & 0x3FF0000) >> 16;
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result[t][6] = (phy_query_bb_reg(adapt, rRx_Power_Before_IQK_B_2,
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bMaskDWord) & 0x3FF0000) >> 16;
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result[t][7] = (phy_query_bb_reg(adapt, rRx_Power_After_IQK_B_2,
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bMaskDWord) & 0x3FF0000) >> 16;
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break;
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} else if (i == (retry_count - 1) && path_b_ok == 0x01) { /* Tx IQK OK */
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result[t][4] = (phy_query_bb_reg(adapt, rTx_Power_Before_IQK_B,
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bMaskDWord) & 0x3FF0000) >> 16;
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result[t][5] = (phy_query_bb_reg(adapt, rTx_Power_After_IQK_B,
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bMaskDWord) & 0x3FF0000) >> 16;
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}
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}
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}
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/* Back to BB mode, load original value */
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phy_set_bb_reg(adapt, rFPGA0_IQK, bMaskDWord, 0);
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@@ -1027,9 +951,6 @@ static void phy_iq_calibrate(struct adapter *adapt, s32 result[][8],
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/* Restore RX initial gain */
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phy_set_bb_reg(adapt, rFPGA0_XA_LSSIParameter,
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bMaskDWord, 0x00032ed3);
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if (is2t)
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phy_set_bb_reg(adapt, rFPGA0_XB_LSSIParameter,
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bMaskDWord, 0x00032ed3);
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/* load 0xe30 IQC default value */
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phy_set_bb_reg(adapt, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00);
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@@ -1133,7 +1054,7 @@ void rtl88eu_phy_iq_calibrate(struct adapter *adapt, bool recovery)
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is13simular = false;
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for (i = 0; i < 3; i++) {
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phy_iq_calibrate(adapt, result, i, false);
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phy_iq_calibrate(adapt, result, i);
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if (i == 1) {
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is12simular = simularity_compare(adapt, result, 0, 1);
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