mirrors/linux
1
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git synced 2026-04-29 10:34:22 -04:00
Code Issues Packages Projects Releases Wiki Activity

drm/amd/display: correct register Clock Gater incorrectly disabled

Browse Source 
[why]
The "dpp35_dppclk_control" routine is incorrectly disabling the register clock gater
when the DPP is enabled.

The "DISPCLK_R_GATE_DISABLE" should never be set to 1 in the normal operating mode.
This will disable the clock gater and the DPPCLK register clock branch will always be running.
As a consequence, the dynamic power will be higher than expected.

Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Charlene Liu
2024-09-11 20:35:39 -04:00
committed by Alex Deucher
parent 1c6b16ebf5
commit a6f59c0445
1 changed files with 4 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c
View File

@@ -50,13 +50,11 @@ void dpp35_dppclk_control(
DPPCLK_RATE_CONTROL, dppclk_div,
DPP_CLOCK_ENABLE, 1);
else
REG_UPDATE_2(DPP_CONTROL,
DPP_CLOCK_ENABLE, 1,
DISPCLK_R_GATE_DISABLE, 1);
REG_UPDATE(DPP_CONTROL,
DPP_CLOCK_ENABLE, 1);
} else
REG_UPDATE_2(DPP_CONTROL,
DPP_CLOCK_ENABLE, 0,
DISPCLK_R_GATE_DISABLE, 0);
REG_UPDATE(DPP_CONTROL,
DPP_CLOCK_ENABLE, 0);
}
void dpp35_program_bias_and_scale_fcnv(