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drm/amd/pm: Add gpu_metrics_v1_5

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Add new gpu_metrics_v1_5 to acquire vcn/jpeg activity
& pcie nak error counters

Signed-off-by: Asad Kamal <asad.kamal@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Le Ma <le.ma@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Asad Kamal
2023-12-20 17:21:48 +08:00
committed by Alex Deucher
parent 9323b4bf6b
commit a62503ca85
2 changed files with 83 additions and 0 deletions
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80
drivers/gpu/drm/amd/include/kgd_pp_interface.h
View File

@@ -318,6 +318,7 @@ enum pp_xgmi_plpd_mode {
#define MAX_GFX_CLKS 8
#define MAX_CLKS 4
#define NUM_VCN 4
#define NUM_JPEG_ENG 32
struct seq_file;
enum amd_pp_clock_type;
@@ -775,6 +776,85 @@ struct gpu_metrics_v1_4 {
uint16_t padding;
};
struct gpu_metrics_v1_5 {
struct metrics_table_header common_header;
/* Temperature (Celsius) */
uint16_t temperature_hotspot;
uint16_t temperature_mem;
uint16_t temperature_vrsoc;
/* Power (Watts) */
uint16_t curr_socket_power;
/* Utilization (%) */
uint16_t average_gfx_activity;
uint16_t average_umc_activity; // memory controller
uint16_t vcn_activity[NUM_VCN];
uint16_t jpeg_activity[NUM_JPEG_ENG];
/* Energy (15.259uJ (2^-16) units) */
uint64_t energy_accumulator;
/* Driver attached timestamp (in ns) */
uint64_t system_clock_counter;
/* Throttle status */
uint32_t throttle_status;
/* Clock Lock Status. Each bit corresponds to clock instance */
uint32_t gfxclk_lock_status;
/* Link width (number of lanes) and speed (in 0.1 GT/s) */
uint16_t pcie_link_width;
uint16_t pcie_link_speed;
/* XGMI bus width and bitrate (in Gbps) */
uint16_t xgmi_link_width;
uint16_t xgmi_link_speed;
/* Utilization Accumulated (%) */
uint32_t gfx_activity_acc;
uint32_t mem_activity_acc;
/*PCIE accumulated bandwidth (GB/sec) */
uint64_t pcie_bandwidth_acc;
/*PCIE instantaneous bandwidth (GB/sec) */
uint64_t pcie_bandwidth_inst;
/* PCIE L0 to recovery state transition accumulated count */
uint64_t pcie_l0_to_recov_count_acc;
/* PCIE replay accumulated count */
uint64_t pcie_replay_count_acc;
/* PCIE replay rollover accumulated count */
uint64_t pcie_replay_rover_count_acc;
/* PCIE NAK sent accumulated count */
uint32_t pcie_nak_sent_count_acc;
/* PCIE NAK received accumulated count */
uint32_t pcie_nak_rcvd_count_acc;
/* XGMI accumulated data transfer size(KiloBytes) */
uint64_t xgmi_read_data_acc[NUM_XGMI_LINKS];
uint64_t xgmi_write_data_acc[NUM_XGMI_LINKS];
/* PMFW attached timestamp (10ns resolution) */
uint64_t firmware_timestamp;
/* Current clocks (Mhz) */
uint16_t current_gfxclk[MAX_GFX_CLKS];
uint16_t current_socclk[MAX_CLKS];
uint16_t current_vclk0[MAX_CLKS];
uint16_t current_dclk0[MAX_CLKS];
uint16_t current_uclk;
uint16_t padding;
};
/*
* gpu_metrics_v2_0 is not recommended as it's not naturally aligned.
* Use gpu_metrics_v2_1 or later instead.

3
drivers/gpu/drm/amd/pm/swsmu/smu_cmn.c
View File

@@ -989,6 +989,9 @@ void smu_cmn_init_soft_gpu_metrics(void *table, uint8_t frev, uint8_t crev)
case METRICS_VERSION(1, 4):
structure_size = sizeof(struct gpu_metrics_v1_4);
break;
case METRICS_VERSION(1, 5):
structure_size = sizeof(struct gpu_metrics_v1_5);
break;
case METRICS_VERSION(2, 0):
structure_size = sizeof(struct gpu_metrics_v2_0);
break;