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arm64: dts: qcom: sm6350: Add pinctrl for SDHCI 2

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Use the generic pin functions specifically for sdc2.

Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Reviewed-by: Luca Weiss <luca.weiss@fairphone.com>
Tested-by: Luca Weiss <luca.weiss@fairphone.com> # sm7225-fairphone-fp4
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221030073232.22726-3-marijn.suijten@somainline.org
This commit is contained in:
Marijn Suijten
2022-10-30 08:32:24 +01:00
committed by Bjorn Andersson
parent e10d451e10
commit a5d0314b9d
1 changed files with 44 additions and 0 deletions
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44
arch/arm64/boot/dts/qcom/sm6350.dtsi
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@@ -1074,6 +1074,10 @@ sdhc_2: mmc@8804000 {
<&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_SDCC_2 0>;
interconnect-names = "sdhc-ddr", "cpu-sdhc";
pinctrl-0 = <&sdc2_on_state>;
pinctrl-1 = <&sdc2_off_state>;
pinctrl-names = "default", "sleep";
qcom,dll-config = <0x0007642c>;
qcom,ddr-config = <0x80040868>;
power-domains = <&rpmhpd SM6350_CX>;
@@ -1313,6 +1317,46 @@ tlmm: pinctrl@f100000 {
#interrupt-cells = <2>;
gpio-ranges = <&tlmm 0 0 157>;
sdc2_off_state: sdc2-off-state {
clk-pins {
pins = "sdc2_clk";
drive-strength = <2>;
bias-disable;
};
cmd-pins {
pins = "sdc2_cmd";
drive-strength = <2>;
bias-pull-up;
};
data-pins {
pins = "sdc2_data";
drive-strength = <2>;
bias-pull-up;
};
};
sdc2_on_state: sdc2-on-state {
clk-pins {
pins = "sdc2_clk";
drive-strength = <16>;
bias-disable;
};
cmd-pins {
pins = "sdc2_cmd";
drive-strength = <10>;
bias-pull-up;
};
data-pins {
pins = "sdc2_data";
drive-strength = <10>;
bias-pull-up;
};
};
qup_uart9_default: qup-uart9-default-state {
pins = "gpio25", "gpio26";
function = "qup13_f2";