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gpio: realtek: Add driver for Realtek DHC RTD1625 SoC
Add support for the GPIO controller found on Realtek DHC RTD1625 SoCs. Unlike the existing Realtek GPIO driver (drivers/gpio/gpio-rtd.c), which manages pins via shared bank registers, the RTD1625 introduces a per-pin register architecture. Each GPIO line now has its own dedicated 32-bit control register to manage configuration independently, including direction, output value, input value, interrupt enable, and debounce. Therefore, this distinct hardware design requires a separate driver. Additionally, the RTD1625 GPIO controller has a specific hardware quirk: it fires both 'assert' and 'de-assert' interrupts simultaneously on any edge toggle. To handle this, we utilize the polarity register to route the requested edge (rising/falling) to the 'assert' IRQ line. The driver then filters out the unwanted 'de-assert' interrupt in the IRQ handler and pre-clears edge interrupts to prevent interrupt storms caused by unhandled dropped interrupts. Interrupt support is optional for this device, matching the dt-bindings. If the interrupts property is not provided, the driver simply skips IRQ initialization and operates purely as a basic GPIO controller. Reviewed-by: Linus Walleij <linusw@kernel.org> Signed-off-by: Tzuyi Chang <tychang@realtek.com> Co-developed-by: Yu-Chun Lin <eleanor.lin@realtek.com> Signed-off-by: Yu-Chun Lin <eleanor.lin@realtek.com> Link: https://patch.msgid.link/20260622092335.1166876-4-eleanor.lin@realtek.com Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@oss.qualcomm.com>
This commit is contained in:
Tzuyi Chang
committed by
Bartosz Golaszewski
Bartosz Golaszewski
parent
b5d23fcdb1
commit
a57e27c43b
@@ -656,6 +656,18 @@ config GPIO_RTD
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Say yes here to support GPIO functionality and GPIO interrupt on
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Realtek DHC SoCs.
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config GPIO_RTD1625
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tristate "Realtek DHC RTD1625 GPIO support"
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depends on ARCH_REALTEK || COMPILE_TEST
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default ARCH_REALTEK
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select GPIOLIB_IRQCHIP
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help
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This option enables support for the GPIO controller on Realtek
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DHC (Digital Home Center) RTD1625 SoC.
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Say yes here to support both basic GPIO line functionality
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and GPIO interrupt handling capabilities for this platform.
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config GPIO_SAMA5D2_PIOBU
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tristate "SAMA5D2 PIOBU GPIO support"
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depends on OF
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@@ -160,6 +160,7 @@ obj-$(CONFIG_GPIO_REALTEK_OTTO) += gpio-realtek-otto.o
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obj-$(CONFIG_GPIO_REG) += gpio-reg.o
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obj-$(CONFIG_GPIO_ROCKCHIP) += gpio-rockchip.o
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obj-$(CONFIG_GPIO_RTD) += gpio-rtd.o
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obj-$(CONFIG_GPIO_RTD1625) += gpio-rtd1625.o
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obj-$(CONFIG_ARCH_SA1100) += gpio-sa1100.o
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obj-$(CONFIG_GPIO_SAMA5D2_PIOBU) += gpio-sama5d2-piobu.o
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obj-$(CONFIG_GPIO_SCH311X) += gpio-sch311x.o
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611
drivers/gpio/gpio-rtd1625.c
Normal file
611
drivers/gpio/gpio-rtd1625.c
Normal file
@@ -0,0 +1,611 @@
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// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Realtek DHC RTD1625 gpio driver
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*
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* Copyright (c) 2023-2026 Realtek Semiconductor Corp.
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*/
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#include <linux/bitfield.h>
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#include <linux/bitops.h>
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#include <linux/cleanup.h>
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#include <linux/gpio/driver.h>
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#include <linux/interrupt.h>
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#include <linux/irqchip.h>
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#include <linux/irqchip/chained_irq.h>
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#include <linux/irqdomain.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/property.h>
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#include <linux/spinlock.h>
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#include <linux/types.h>
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#define RTD1625_GPIO_DIR BIT(0)
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#define RTD1625_GPIO_OUT BIT(2)
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#define RTD1625_GPIO_IN BIT(4)
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#define RTD1625_GPIO_EDGE_INT_DP BIT(6)
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#define RTD1625_GPIO_EDGE_INT_EN BIT(8)
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#define RTD1625_GPIO_LEVEL_INT_EN BIT(16)
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#define RTD1625_GPIO_LEVEL_INT_DP BIT(18)
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#define RTD1625_GPIO_DEBOUNCE GENMASK(30, 28)
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#define RTD1625_GPIO_DEBOUNCE_WREN BIT(31)
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#define RTD1625_GPIO_WREN(x) ((x) << 1)
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/* Write-enable masks for all GPIO configs and reserved hardware bits */
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#define RTD1625_ISO_GPIO_WREN_ALL 0x8000aa8a
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#define RTD1625_ISOM_GPIO_WREN_ALL 0x800aaa8a
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#define RTD1625_GPIO_DEBOUNCE_1US 0
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#define RTD1625_GPIO_DEBOUNCE_10US 1
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#define RTD1625_GPIO_DEBOUNCE_100US 2
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#define RTD1625_GPIO_DEBOUNCE_1MS 3
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#define RTD1625_GPIO_DEBOUNCE_10MS 4
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#define RTD1625_GPIO_DEBOUNCE_20MS 5
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#define RTD1625_GPIO_DEBOUNCE_30MS 6
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#define RTD1625_GPIO_DEBOUNCE_50MS 7
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#define GPIO_CONTROL(gpio) ((gpio) * 4)
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enum rtd1625_irq_index {
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RTD1625_IRQ_ASSERT,
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RTD1625_IRQ_DEASSERT,
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RTD1625_IRQ_LEVEL,
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RTD1625_MAX_IRQS
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};
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/**
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* struct rtd1625_gpio_info - Specific GPIO register information
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* @num_gpios: The number of GPIOs
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* @irq_type_support: Supported IRQ types
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* @gpa_offset: Offset for GPIO assert interrupt status registers
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* @gpda_offset: Offset for GPIO deassert interrupt status registers
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* @level_offset: Offset of level interrupt status register
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* @write_en_all: Write-enable mask for all configurable bits
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*/
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struct rtd1625_gpio_info {
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unsigned int num_gpios;
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unsigned int irq_type_support;
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unsigned int base_offset;
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unsigned int gpa_offset;
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unsigned int gpda_offset;
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unsigned int level_offset;
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unsigned int write_en_all;
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};
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struct rtd1625_gpio {
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struct gpio_chip gpio_chip;
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const struct rtd1625_gpio_info *info;
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void __iomem *base;
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void __iomem *irq_base;
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unsigned int irqs[RTD1625_MAX_IRQS];
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raw_spinlock_t lock;
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unsigned int *save_regs;
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};
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static unsigned int rtd1625_gpio_gpa_offset(struct rtd1625_gpio *data, unsigned int offset)
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{
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return data->info->gpa_offset + ((offset / 32) * 4);
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}
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static unsigned int rtd1625_gpio_gpda_offset(struct rtd1625_gpio *data, unsigned int offset)
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{
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return data->info->gpda_offset + ((offset / 32) * 4);
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}
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static unsigned int rtd1625_gpio_level_offset(struct rtd1625_gpio *data, unsigned int offset)
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{
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return data->info->level_offset + ((offset / 32) * 4);
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}
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static int rtd1625_gpio_set_debounce(struct gpio_chip *chip, unsigned int offset,
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unsigned int debounce)
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{
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struct rtd1625_gpio *data = gpiochip_get_data(chip);
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u8 deb_val;
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u32 val;
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switch (debounce) {
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case 1:
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deb_val = RTD1625_GPIO_DEBOUNCE_1US;
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break;
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case 10:
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deb_val = RTD1625_GPIO_DEBOUNCE_10US;
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break;
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case 100:
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deb_val = RTD1625_GPIO_DEBOUNCE_100US;
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break;
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case 1000:
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deb_val = RTD1625_GPIO_DEBOUNCE_1MS;
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break;
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case 10000:
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deb_val = RTD1625_GPIO_DEBOUNCE_10MS;
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break;
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case 20000:
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deb_val = RTD1625_GPIO_DEBOUNCE_20MS;
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break;
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case 30000:
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deb_val = RTD1625_GPIO_DEBOUNCE_30MS;
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break;
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case 50000:
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deb_val = RTD1625_GPIO_DEBOUNCE_50MS;
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break;
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default:
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return -ENOTSUPP;
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}
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val = FIELD_PREP(RTD1625_GPIO_DEBOUNCE, deb_val) | RTD1625_GPIO_DEBOUNCE_WREN;
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guard(raw_spinlock_irqsave)(&data->lock);
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writel_relaxed(val, data->base + GPIO_CONTROL(offset));
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return 0;
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}
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static int rtd1625_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
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unsigned long config)
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{
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u32 debounce;
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if (pinconf_to_config_param(config) == PIN_CONFIG_INPUT_DEBOUNCE) {
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debounce = pinconf_to_config_argument(config);
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return rtd1625_gpio_set_debounce(chip, offset, debounce);
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}
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return gpiochip_generic_config(chip, offset, config);
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}
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static int rtd1625_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
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{
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struct rtd1625_gpio *data = gpiochip_get_data(chip);
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u32 val = RTD1625_GPIO_WREN(RTD1625_GPIO_OUT);
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if (value)
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val |= RTD1625_GPIO_OUT;
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guard(raw_spinlock_irqsave)(&data->lock);
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writel_relaxed(val, data->base + GPIO_CONTROL(offset));
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return 0;
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}
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static int rtd1625_gpio_get(struct gpio_chip *chip, unsigned int offset)
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{
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struct rtd1625_gpio *data = gpiochip_get_data(chip);
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u32 val;
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guard(raw_spinlock_irqsave)(&data->lock);
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val = readl_relaxed(data->base + GPIO_CONTROL(offset));
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if (val & RTD1625_GPIO_DIR)
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return !!(val & RTD1625_GPIO_OUT);
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else
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return !!(val & RTD1625_GPIO_IN);
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}
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static int rtd1625_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
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{
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struct rtd1625_gpio *data = gpiochip_get_data(chip);
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u32 val;
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guard(raw_spinlock_irqsave)(&data->lock);
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val = readl_relaxed(data->base + GPIO_CONTROL(offset));
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if (val & RTD1625_GPIO_DIR)
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return GPIO_LINE_DIRECTION_OUT;
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return GPIO_LINE_DIRECTION_IN;
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}
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static int rtd1625_gpio_set_direction(struct gpio_chip *chip, unsigned int offset, bool out)
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{
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struct rtd1625_gpio *data = gpiochip_get_data(chip);
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u32 val = RTD1625_GPIO_WREN(RTD1625_GPIO_DIR);
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if (out)
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val |= RTD1625_GPIO_DIR;
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guard(raw_spinlock_irqsave)(&data->lock);
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writel_relaxed(val, data->base + GPIO_CONTROL(offset));
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return 0;
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}
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static int rtd1625_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
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{
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return rtd1625_gpio_set_direction(chip, offset, false);
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}
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static int rtd1625_gpio_direction_output(struct gpio_chip *chip, unsigned int offset, int value)
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{
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rtd1625_gpio_set(chip, offset, value);
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return rtd1625_gpio_set_direction(chip, offset, true);
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}
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static void rtd1625_gpio_irq_handle(struct irq_desc *desc)
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{
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unsigned int (*get_reg_offset)(struct rtd1625_gpio *gpio, unsigned int offset);
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struct rtd1625_gpio *data = irq_desc_get_handler_data(desc);
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struct irq_domain *domain = data->gpio_chip.irq.domain;
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struct irq_chip *chip = irq_desc_get_chip(desc);
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unsigned int irq = irq_desc_get_irq(desc);
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unsigned long status;
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unsigned int reg_offset, i, j;
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unsigned int girq;
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irq_hw_number_t hwirq;
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u32 irq_type;
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if (irq == data->irqs[RTD1625_IRQ_ASSERT])
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get_reg_offset = &rtd1625_gpio_gpa_offset;
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else if (irq == data->irqs[RTD1625_IRQ_DEASSERT])
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get_reg_offset = &rtd1625_gpio_gpda_offset;
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else if (irq == data->irqs[2])
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get_reg_offset = &rtd1625_gpio_level_offset;
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else
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return;
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chained_irq_enter(chip, desc);
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for (i = 0; i < data->info->num_gpios; i += 32) {
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reg_offset = get_reg_offset(data, i);
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status = readl_relaxed(data->irq_base + reg_offset);
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/*
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* Hardware quirk: The controller fires both "assert" and "de-assert"
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* interrupts simultaneously on any edge toggle.
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* We must pre-clear edge interrupts here. If we drop an unwanted
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* de-assert interrupt below, it will never reach the IRQ core
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* (generic_handle_domain_irq), meaning ->irq_ack() won't be called.
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* Failing to clear it here leads to an interrupt storm.
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*/
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if (irq != data->irqs[RTD1625_IRQ_LEVEL])
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writel_relaxed(status, data->irq_base + reg_offset);
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for_each_set_bit(j, &status, 32) {
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hwirq = i + j;
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girq = irq_find_mapping(domain, hwirq);
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irq_type = irq_get_trigger_type(girq);
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/*
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* Filter out the hardware-forced de-assert interrupt unless
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* the user explicitly requested IRQ_TYPE_EDGE_BOTH.
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*/
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if (irq == data->irqs[RTD1625_IRQ_DEASSERT] &&
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irq_type != IRQ_TYPE_EDGE_BOTH)
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continue;
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generic_handle_domain_irq(domain, hwirq);
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}
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}
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chained_irq_exit(chip, desc);
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}
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static void rtd1625_gpio_ack_irq(struct irq_data *d)
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{
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struct rtd1625_gpio *data = irq_data_get_irq_chip_data(d);
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irq_hw_number_t hwirq = irqd_to_hwirq(d);
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u32 irq_type = irqd_get_trigger_type(d);
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u32 bit_mask = BIT(hwirq % 32);
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int reg_offset;
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if (irq_type & IRQ_TYPE_LEVEL_MASK) {
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reg_offset = rtd1625_gpio_level_offset(data, hwirq);
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writel_relaxed(bit_mask, data->irq_base + reg_offset);
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}
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}
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static void rtd1625_gpio_enable_edge_irq(struct rtd1625_gpio *data, irq_hw_number_t hwirq)
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{
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int gpda_reg_offset = rtd1625_gpio_gpda_offset(data, hwirq);
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int gpa_reg_offset = rtd1625_gpio_gpa_offset(data, hwirq);
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u32 clr_mask = BIT(hwirq % 32);
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u32 val;
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guard(raw_spinlock_irqsave)(&data->lock);
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writel_relaxed(clr_mask, data->irq_base + gpa_reg_offset);
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writel_relaxed(clr_mask, data->irq_base + gpda_reg_offset);
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val = RTD1625_GPIO_EDGE_INT_EN | RTD1625_GPIO_WREN(RTD1625_GPIO_EDGE_INT_EN);
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writel_relaxed(val, data->base + GPIO_CONTROL(hwirq));
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}
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static void rtd1625_gpio_disable_edge_irq(struct rtd1625_gpio *data, irq_hw_number_t hwirq)
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{
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u32 val;
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guard(raw_spinlock_irqsave)(&data->lock);
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val = RTD1625_GPIO_WREN(RTD1625_GPIO_EDGE_INT_EN);
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writel_relaxed(val, data->base + GPIO_CONTROL(hwirq));
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}
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static void rtd1625_gpio_enable_level_irq(struct rtd1625_gpio *data, irq_hw_number_t hwirq)
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{
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int level_reg_offset = rtd1625_gpio_level_offset(data, hwirq);
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u32 clr_mask = BIT(hwirq % 32);
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u32 val;
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guard(raw_spinlock_irqsave)(&data->lock);
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writel_relaxed(clr_mask, data->irq_base + level_reg_offset);
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val = RTD1625_GPIO_LEVEL_INT_EN | RTD1625_GPIO_WREN(RTD1625_GPIO_LEVEL_INT_EN);
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writel_relaxed(val, data->base + GPIO_CONTROL(hwirq));
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}
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static void rtd1625_gpio_disable_level_irq(struct rtd1625_gpio *data, irq_hw_number_t hwirq)
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{
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u32 val;
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guard(raw_spinlock_irqsave)(&data->lock);
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val = RTD1625_GPIO_WREN(RTD1625_GPIO_LEVEL_INT_EN);
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writel_relaxed(val, data->base + GPIO_CONTROL(hwirq));
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}
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static void rtd1625_gpio_enable_irq(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct rtd1625_gpio *data = gpiochip_get_data(gc);
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irq_hw_number_t hwirq = irqd_to_hwirq(d);
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u32 irq_type = irqd_get_trigger_type(d);
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gpiochip_enable_irq(gc, hwirq);
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if (irq_type & IRQ_TYPE_EDGE_BOTH)
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rtd1625_gpio_enable_edge_irq(data, hwirq);
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else if (irq_type & IRQ_TYPE_LEVEL_MASK)
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rtd1625_gpio_enable_level_irq(data, hwirq);
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}
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static void rtd1625_gpio_disable_irq(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct rtd1625_gpio *data = gpiochip_get_data(gc);
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irq_hw_number_t hwirq = irqd_to_hwirq(d);
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u32 irq_type = irqd_get_trigger_type(d);
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if (irq_type & IRQ_TYPE_EDGE_BOTH)
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rtd1625_gpio_disable_edge_irq(data, hwirq);
|
||||
else if (irq_type & IRQ_TYPE_LEVEL_MASK)
|
||||
rtd1625_gpio_disable_level_irq(data, hwirq);
|
||||
|
||||
gpiochip_disable_irq(gc, hwirq);
|
||||
}
|
||||
|
||||
static int rtd1625_gpio_irq_set_level_type(struct irq_data *d, bool level)
|
||||
{
|
||||
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
|
||||
struct rtd1625_gpio *data = gpiochip_get_data(gc);
|
||||
irq_hw_number_t hwirq = irqd_to_hwirq(d);
|
||||
u32 val = RTD1625_GPIO_WREN(RTD1625_GPIO_LEVEL_INT_DP);
|
||||
|
||||
if (!(data->info->irq_type_support & IRQ_TYPE_LEVEL_MASK))
|
||||
return -EINVAL;
|
||||
|
||||
if (level)
|
||||
val |= RTD1625_GPIO_LEVEL_INT_DP;
|
||||
|
||||
scoped_guard(raw_spinlock_irqsave, &data->lock)
|
||||
writel_relaxed(val, data->base + GPIO_CONTROL(hwirq));
|
||||
|
||||
irq_set_handler_locked(d, handle_level_irq);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rtd1625_gpio_irq_set_edge_type(struct irq_data *d, bool polarity)
|
||||
{
|
||||
struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
|
||||
struct rtd1625_gpio *data = gpiochip_get_data(gc);
|
||||
irq_hw_number_t hwirq = irqd_to_hwirq(d);
|
||||
u32 val = RTD1625_GPIO_WREN(RTD1625_GPIO_EDGE_INT_DP);
|
||||
|
||||
if (!(data->info->irq_type_support & IRQ_TYPE_EDGE_BOTH))
|
||||
return -EINVAL;
|
||||
|
||||
if (polarity)
|
||||
val |= RTD1625_GPIO_EDGE_INT_DP;
|
||||
|
||||
scoped_guard(raw_spinlock_irqsave, &data->lock)
|
||||
writel_relaxed(val, data->base + GPIO_CONTROL(hwirq));
|
||||
|
||||
irq_set_handler_locked(d, handle_edge_irq);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rtd1625_gpio_irq_set_type(struct irq_data *d, unsigned int type)
|
||||
{
|
||||
switch (type & IRQ_TYPE_SENSE_MASK) {
|
||||
case IRQ_TYPE_EDGE_RISING:
|
||||
return rtd1625_gpio_irq_set_edge_type(d, 1);
|
||||
|
||||
case IRQ_TYPE_EDGE_FALLING:
|
||||
return rtd1625_gpio_irq_set_edge_type(d, 0);
|
||||
|
||||
case IRQ_TYPE_EDGE_BOTH:
|
||||
return rtd1625_gpio_irq_set_edge_type(d, 1);
|
||||
|
||||
case IRQ_TYPE_LEVEL_HIGH:
|
||||
return rtd1625_gpio_irq_set_level_type(d, 0);
|
||||
|
||||
case IRQ_TYPE_LEVEL_LOW:
|
||||
return rtd1625_gpio_irq_set_level_type(d, 1);
|
||||
|
||||
default:
|
||||
return -EINVAL;
|
||||
}
|
||||
}
|
||||
|
||||
static struct irq_chip rtd1625_iso_gpio_irq_chip = {
|
||||
.name = "rtd1625-gpio",
|
||||
.irq_ack = rtd1625_gpio_ack_irq,
|
||||
.irq_mask = rtd1625_gpio_disable_irq,
|
||||
.irq_unmask = rtd1625_gpio_enable_irq,
|
||||
.irq_set_type = rtd1625_gpio_irq_set_type,
|
||||
.flags = IRQCHIP_IMMUTABLE | IRQCHIP_SKIP_SET_WAKE,
|
||||
GPIOCHIP_IRQ_RESOURCE_HELPERS,
|
||||
};
|
||||
|
||||
static int rtd1625_gpio_setup_irq(struct platform_device *pdev, struct rtd1625_gpio *data)
|
||||
{
|
||||
struct gpio_irq_chip *irq_chip;
|
||||
unsigned int num_irqs;
|
||||
int irq;
|
||||
|
||||
/*
|
||||
* Interrupt support is optional. All IRQs must be provided together.
|
||||
* If index 0 is missing, we assume no interrupts are configured in DT
|
||||
* and fall back to basic GPIO operation.
|
||||
*/
|
||||
irq = platform_get_irq_optional(pdev, 0);
|
||||
if (irq == -ENXIO)
|
||||
return 0;
|
||||
if (irq < 0)
|
||||
return irq;
|
||||
|
||||
num_irqs = (data->info->irq_type_support & IRQ_TYPE_LEVEL_MASK) ? 3 : 2;
|
||||
data->irqs[RTD1625_IRQ_ASSERT] = irq;
|
||||
|
||||
for (unsigned int i = 1; i < num_irqs; i++) {
|
||||
irq = platform_get_irq(pdev, i);
|
||||
if (irq < 0)
|
||||
return irq;
|
||||
data->irqs[i] = irq;
|
||||
}
|
||||
|
||||
irq_chip = &data->gpio_chip.irq;
|
||||
irq_chip->handler = handle_bad_irq;
|
||||
irq_chip->default_type = IRQ_TYPE_NONE;
|
||||
irq_chip->parent_handler = rtd1625_gpio_irq_handle;
|
||||
irq_chip->parent_handler_data = data;
|
||||
irq_chip->num_parents = num_irqs;
|
||||
irq_chip->parents = data->irqs;
|
||||
|
||||
gpio_irq_chip_set_chip(irq_chip, &rtd1625_iso_gpio_irq_chip);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rtd1625_gpio_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct rtd1625_gpio *data;
|
||||
void __iomem *irq_base;
|
||||
int ret;
|
||||
|
||||
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
|
||||
if (!data)
|
||||
return -ENOMEM;
|
||||
|
||||
data->info = device_get_match_data(dev);
|
||||
if (!data->info)
|
||||
return -EINVAL;
|
||||
|
||||
raw_spin_lock_init(&data->lock);
|
||||
|
||||
irq_base = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(irq_base))
|
||||
return PTR_ERR(irq_base);
|
||||
|
||||
data->irq_base = irq_base;
|
||||
data->base = irq_base + data->info->base_offset;
|
||||
|
||||
data->save_regs = devm_kcalloc(dev, data->info->num_gpios, sizeof(*data->save_regs),
|
||||
GFP_KERNEL);
|
||||
if (!data->save_regs)
|
||||
return -ENOMEM;
|
||||
|
||||
data->gpio_chip.label = dev_name(dev);
|
||||
data->gpio_chip.base = -1;
|
||||
data->gpio_chip.ngpio = data->info->num_gpios;
|
||||
data->gpio_chip.request = gpiochip_generic_request;
|
||||
data->gpio_chip.free = gpiochip_generic_free;
|
||||
data->gpio_chip.get_direction = rtd1625_gpio_get_direction;
|
||||
data->gpio_chip.direction_input = rtd1625_gpio_direction_input;
|
||||
data->gpio_chip.direction_output = rtd1625_gpio_direction_output;
|
||||
data->gpio_chip.set = rtd1625_gpio_set;
|
||||
data->gpio_chip.get = rtd1625_gpio_get;
|
||||
data->gpio_chip.set_config = rtd1625_gpio_set_config;
|
||||
data->gpio_chip.parent = dev;
|
||||
|
||||
ret = rtd1625_gpio_setup_irq(pdev, data);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
platform_set_drvdata(pdev, data);
|
||||
|
||||
return devm_gpiochip_add_data(dev, &data->gpio_chip, data);
|
||||
}
|
||||
|
||||
static const struct rtd1625_gpio_info rtd1625_iso_gpio_info = {
|
||||
.num_gpios = 166,
|
||||
.irq_type_support = IRQ_TYPE_EDGE_BOTH,
|
||||
.base_offset = 0x100,
|
||||
.gpa_offset = 0x000,
|
||||
.gpda_offset = 0x020,
|
||||
.write_en_all = RTD1625_ISO_GPIO_WREN_ALL,
|
||||
};
|
||||
|
||||
static const struct rtd1625_gpio_info rtd1625_isom_gpio_info = {
|
||||
.num_gpios = 4,
|
||||
.irq_type_support = IRQ_TYPE_EDGE_BOTH | IRQ_TYPE_LEVEL_LOW |
|
||||
IRQ_TYPE_LEVEL_HIGH,
|
||||
.base_offset = 0x20,
|
||||
.gpa_offset = 0x00,
|
||||
.gpda_offset = 0x04,
|
||||
.level_offset = 0x18,
|
||||
.write_en_all = RTD1625_ISOM_GPIO_WREN_ALL,
|
||||
};
|
||||
|
||||
static int rtd1625_gpio_suspend(struct device *dev)
|
||||
{
|
||||
struct rtd1625_gpio *data = dev_get_drvdata(dev);
|
||||
const struct rtd1625_gpio_info *info = data->info;
|
||||
|
||||
for (unsigned int i = 0; i < info->num_gpios; i++)
|
||||
data->save_regs[i] = readl_relaxed(data->base + GPIO_CONTROL(i));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rtd1625_gpio_resume(struct device *dev)
|
||||
{
|
||||
struct rtd1625_gpio *data = dev_get_drvdata(dev);
|
||||
const struct rtd1625_gpio_info *info = data->info;
|
||||
|
||||
for (unsigned int i = 0; i < info->num_gpios; i++)
|
||||
writel_relaxed(data->save_regs[i] | info->write_en_all,
|
||||
data->base + GPIO_CONTROL(i));
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static DEFINE_NOIRQ_DEV_PM_OPS(rtd1625_gpio_pm_ops, rtd1625_gpio_suspend, rtd1625_gpio_resume);
|
||||
|
||||
static const struct of_device_id rtd1625_gpio_of_matches[] = {
|
||||
{ .compatible = "realtek,rtd1625-iso-gpio", .data = &rtd1625_iso_gpio_info },
|
||||
{ .compatible = "realtek,rtd1625-isom-gpio", .data = &rtd1625_isom_gpio_info },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, rtd1625_gpio_of_matches);
|
||||
|
||||
static struct platform_driver rtd1625_gpio_platform_driver = {
|
||||
.driver = {
|
||||
.name = "gpio-rtd1625",
|
||||
.of_match_table = rtd1625_gpio_of_matches,
|
||||
.pm = pm_sleep_ptr(&rtd1625_gpio_pm_ops),
|
||||
},
|
||||
.probe = rtd1625_gpio_probe,
|
||||
};
|
||||
module_platform_driver(rtd1625_gpio_platform_driver);
|
||||
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_AUTHOR("Realtek Semiconductor Corporation");
|
||||
MODULE_DESCRIPTION("Realtek DHC SoC RTD1625 gpio driver");
|
||||
Reference in New Issue
Block a user