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mlxsw: reg: Add Port Module Type Mapping Register
The PMTM allows query or configuration of module types. Signed-off-by: Jiri Pirko <jiri@mellanox.com> Reviewed-by: Shalom Toledo <shalomt@mellanox.com> Signed-off-by: Ido Schimmel <idosch@mellanox.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
committed by
David S. Miller
parent
94e768373a
commit
a513b1a591
@@ -5375,6 +5375,55 @@ static inline void mlxsw_reg_pplr_pack(char *payload, u8 local_port,
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MLXSW_REG_PPLR_LB_TYPE_BIT_PHY_LOCAL : 0);
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}
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/* PMTM - Port Module Type Mapping Register
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* ----------------------------------------
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* The PMTM allows query or configuration of module types.
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*/
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#define MLXSW_REG_PMTM_ID 0x5067
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#define MLXSW_REG_PMTM_LEN 0x10
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MLXSW_REG_DEFINE(pmtm, MLXSW_REG_PMTM_ID, MLXSW_REG_PMTM_LEN);
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/* reg_pmtm_module
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* Module number.
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* Access: Index
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*/
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MLXSW_ITEM32(reg, pmtm, module, 0x00, 16, 8);
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enum mlxsw_reg_pmtm_module_type {
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/* Backplane with 4 lanes */
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MLXSW_REG_PMTM_MODULE_TYPE_BP_4X,
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/* QSFP */
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MLXSW_REG_PMTM_MODULE_TYPE_BP_QSFP,
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/* SFP */
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MLXSW_REG_PMTM_MODULE_TYPE_BP_SFP,
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/* Backplane with single lane */
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MLXSW_REG_PMTM_MODULE_TYPE_BP_1X = 4,
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/* Backplane with two lane */
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MLXSW_REG_PMTM_MODULE_TYPE_BP_2X = 8,
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/* Chip2Chip */
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MLXSW_REG_PMTM_MODULE_TYPE_C2C = 10,
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};
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/* reg_pmtm_module_type
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* Module type.
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* Access: RW
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*/
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MLXSW_ITEM32(reg, pmtm, module_type, 0x04, 0, 4);
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static inline void mlxsw_reg_pmtm_pack(char *payload, u8 module)
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{
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MLXSW_REG_ZERO(pmtm, payload);
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mlxsw_reg_pmtm_module_set(payload, module);
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}
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static inline void
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mlxsw_reg_pmtm_unpack(char *payload,
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enum mlxsw_reg_pmtm_module_type *module_type)
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{
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*module_type = mlxsw_reg_pmtm_module_type_get(payload);
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}
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/* HTGT - Host Trap Group Table
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* ----------------------------
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* Configures the properties for forwarding to CPU.
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@@ -10545,6 +10594,7 @@ static const struct mlxsw_reg_info *mlxsw_reg_infos[] = {
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MLXSW_REG(pbmc),
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MLXSW_REG(pspa),
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MLXSW_REG(pplr),
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MLXSW_REG(pmtm),
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MLXSW_REG(htgt),
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MLXSW_REG(hpkt),
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MLXSW_REG(rgcr),
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