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Merge tag 'hisi-arm64-dt-for-6.6' of https://github.com/hisilicon/linux-hisi into soc/dt

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ARM64: DT: HiSilicon ARM64 DT updates for v6.6

- Miscellaneous fixes according the DTS coding style
- Correct the clocks order of the sd0 for the hi3798cv200

* tag 'hisi-arm64-dt-for-6.6' of https://github.com/hisilicon/linux-hisi:
  arm64: dts: hi3798cv200: Fix clocks order of sd0
  arm64: dts: hisilicon: add missing space before {
  arm64: dts: hisilicon: minor whitespace cleanup around '='

Link: https://lore.kernel.org/r/64CC99A3.5030701@hisilicon.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2023-08-12 10:42:44 +02:00
parent a6fb5573a3 dc8cbdd9c6
commit a4cd6f2677
4 changed files with 22 additions and 22 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
View File

@@ -302,8 +302,8 @@ sd0: mmc@9820000 {
compatible = "snps,dw-mshc";
reg = <0x9820000 0x10000>;
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg HISTB_SDIO0_CIU_CLK>,
<&crg HISTB_SDIO0_BIU_CLK>;
clocks = <&crg HISTB_SDIO0_BIU_CLK>,
<&crg HISTB_SDIO0_CIU_CLK>;
clock-names = "biu", "ciu";
resets = <&crg 0x9c 4>;
reset-names = "reset";

24
arch/arm64/boot/dts/hisilicon/hi6220.dtsi
View File

@@ -861,7 +861,7 @@ tsensor: tsensor@0,f7030700 {
#thermal-sensor-cells = <1>;
};
i2s0: i2s@f7118000{
i2s0: i2s@f7118000 {
compatible = "hisilicon,hi6210-i2s";
reg = <0x0 0xf7118000 0x0 0x8000>; /* i2s unit */
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; /* 155 "DigACodec_intr"-32 */
@@ -1032,17 +1032,17 @@ mali: gpu@f4080000 {
compatible = "hisilicon,hi6220-mali", "arm,mali-450";
reg = <0x0 0xf4080000 0x0 0x00040000>;
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>;
interrupts = <GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>,
<GIC_PPI 126 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "gp",
"gpmmu",

8
arch/arm64/boot/dts/hisilicon/hip06.dtsi
View File

@@ -570,7 +570,7 @@ port@5 {
};
};
eth0: ethernet-4{
eth0: ethernet-4 {
compatible = "hisilicon,hns-nic-v2";
ae-handle = <&dsaf0>;
port-idx-in-ae = <4>;
@@ -579,7 +579,7 @@ eth0: ethernet-4{
dma-coherent;
};
eth1: ethernet-5{
eth1: ethernet-5 {
compatible = "hisilicon,hns-nic-v2";
ae-handle = <&dsaf0>;
port-idx-in-ae = <5>;
@@ -588,7 +588,7 @@ eth1: ethernet-5{
dma-coherent;
};
eth2: ethernet-0{
eth2: ethernet-0 {
compatible = "hisilicon,hns-nic-v2";
ae-handle = <&dsaf0>;
port-idx-in-ae = <0>;
@@ -597,7 +597,7 @@ eth2: ethernet-0{
dma-coherent;
};
eth3: ethernet-1{
eth3: ethernet-1 {
compatible = "hisilicon,hns-nic-v2";
ae-handle = <&dsaf0>;
port-idx-in-ae = <1>;

8
arch/arm64/boot/dts/hisilicon/hip07.dtsi
View File

@@ -1483,7 +1483,7 @@ port@5 {
};
};
eth0: ethernet@4{
eth0: ethernet@4 {
compatible = "hisilicon,hns-nic-v2";
ae-handle = <&dsaf0>;
port-idx-in-ae = <4>;
@@ -1492,7 +1492,7 @@ eth0: ethernet@4{
dma-coherent;
};
eth1: ethernet@5{
eth1: ethernet@5 {
compatible = "hisilicon,hns-nic-v2";
ae-handle = <&dsaf0>;
port-idx-in-ae = <5>;
@@ -1501,7 +1501,7 @@ eth1: ethernet@5{
dma-coherent;
};
eth2: ethernet@0{
eth2: ethernet@0 {
compatible = "hisilicon,hns-nic-v2";
ae-handle = <&dsaf0>;
port-idx-in-ae = <0>;
@@ -1510,7 +1510,7 @@ eth2: ethernet@0{
dma-coherent;
};
eth3: ethernet@1{
eth3: ethernet@1 {
compatible = "hisilicon,hns-nic-v2";
ae-handle = <&dsaf0>;
port-idx-in-ae = <1>;