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drm/i915/fbc: Nuke BDW_FBC_COMP_SEG_MASK

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Just use a same mask for ivb/hsw as for bdw+. The extra bit
in the bdw mask is mbz on ivb/hsw anyway so this is just
pointless complexity.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211104144520.22605-12-ville.syrjala@linux.intel.com
Acked-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
This commit is contained in:
Ville Syrjälä
2021-11-04 16:45:14 +02:00
parent a61cf3883c
commit a465538370
2 changed files with 2 additions and 6 deletions
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5
drivers/gpu/drm/i915/display/intel_fbc.c
View File

@@ -533,10 +533,7 @@ static void ivb_fbc_activate(struct drm_i915_private *dev_priv)
static bool ivb_fbc_is_compressing(struct drm_i915_private *i915)
{
if (DISPLAY_VER(i915) >= 8)
return intel_de_read(i915, IVB_FBC_STATUS2) & BDW_FBC_COMP_SEG_MASK;
else
return intel_de_read(i915, IVB_FBC_STATUS2) & IVB_FBC_COMP_SEG_MASK;
return intel_de_read(i915, IVB_FBC_STATUS2) & IVB_FBC_COMP_SEG_MASK;
}
static void ivb_fbc_set_false_color(struct drm_i915_private *i915,

3
drivers/gpu/drm/i915/i915_reg.h
View File

@@ -3380,8 +3380,7 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
#define ILK_DPFC_STATUS _MMIO(0x43210)
#define ILK_DPFC_COMP_SEG_MASK 0x7ff
#define IVB_FBC_STATUS2 _MMIO(0x43214)
#define IVB_FBC_COMP_SEG_MASK 0x7ff
#define BDW_FBC_COMP_SEG_MASK 0xfff
#define IVB_FBC_COMP_SEG_MASK 0xfff
#define ILK_DPFC_FENCE_YOFF _MMIO(0x43218)
#define ILK_DPFC_CHICKEN _MMIO(0x43224)
#define ILK_DPFC_DISABLE_DUMMY0 (1 << 8)