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drm/xe/xe2: Add workaround 14020013138
This workaround applies to Xe2_LPG A0 V3: - Apply rule RENDER class V2(Matt): - Apply WA in lrc context Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Tejas Upadhyay <tejas.upadhyay@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
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committed by
Rodrigo Vivi
parent
f91bacce8d
commit
a409901f51
@@ -93,6 +93,9 @@
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#define XEHP_TILE_ADDR_RANGE(_idx) XE_REG_MCR(0x4900 + (_idx) * 4)
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#define XEHP_FLAT_CCS_BASE_ADDR XE_REG_MCR(0x4910)
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#define WM_CHICKEN3 XE_REG_MCR(0x5588, XE_REG_OPTION_MASKED)
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#define HIZ_PLANE_COMPRESSION_DIS REG_BIT(10)
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#define CHICKEN_RASTER_2 XE_REG_MCR(0x6208, XE_REG_OPTION_MASKED)
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#define TBIMR_FAST_CLIP REG_BIT(5)
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@@ -714,6 +714,11 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
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XE_RTP_RULES(GRAPHICS_VERSION(2004), ENGINE_CLASS(RENDER)),
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XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))
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},
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{ XE_RTP_NAME("14020013138"),
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XE_RTP_RULES(GRAPHICS_VERSION(2004), GRAPHICS_STEP(A0, B0),
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ENGINE_CLASS(RENDER)),
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XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS))
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},
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{}
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};
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