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x86/mce: Add Xeon Sapphire Rapids to list of CPUs that support PPIN

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New CPU model, same MSRs to control and read the inventory number.

Signed-off-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Link: https://lore.kernel.org/r/20210319173919.291428-1-tony.luck@intel.com
This commit is contained in:
Tony Luck
2021-03-19 10:39:19 -07:00
committed by Ingo Molnar
parent 301cddc21a
commit a331f5fdd3
1 changed files with 1 additions and 0 deletions
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arch/x86/kernel/cpu/mce/intel.c
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@@ -486,6 +486,7 @@ static void intel_ppin_init(struct cpuinfo_x86 *c)
case INTEL_FAM6_BROADWELL_X:
case INTEL_FAM6_SKYLAKE_X:
case INTEL_FAM6_ICELAKE_X:
case INTEL_FAM6_SAPPHIRERAPIDS_X:
case INTEL_FAM6_XEON_PHI_KNL:
case INTEL_FAM6_XEON_PHI_KNM: