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Merge tag 'ti-k3-dt-for-v5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux into arm/dt
Texas Instruments K3 SoC DT updates for v5.8 - Add DSS support for both AM65x and J721e - Add watchdog support for J721e - Add EHRPWM support for AM65x - Add Thermal support for AM65x * tag 'ti-k3-dt-for-v5.8' of git://git.kernel.org/pub/scm/linux/kernel/git/kristo/linux: arm64: dts: ti: k3-j721e-main: Add main domain watchdog entries arm64: dts: ti: k3-am65-main: Add ehrpwm nodes arm64: dts: ti: am654: Add thermal zones arm64: dts: ti: am65-wakeup: Add VTM node arm64: dts: ti: k3-j721e-common-proc-board: add assigned clks for DSS arm64: dts: ti: k3-j721e-main: Add DSS node arm64: dts: ti: am654: Add DSS node Link: https://lore.kernel.org/r/7484d3c9-323f-36a3-f0df-1287586f356d@ti.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
@@ -287,6 +287,17 @@ serdes_mux: mux-controller {
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mux-reg-masks = <0x4080 0x3>, /* SERDES0 lane select */
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<0x4090 0x3>; /* SERDES1 lane select */
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};
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dss_oldi_io_ctrl: dss_oldi_io_ctrl@41E0 {
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compatible = "syscon";
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reg = <0x0000041E0 0x14>;
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};
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ehrpwm_tbclk: syscon@4140 {
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compatible = "ti,am654-ehrpwm-tbclk", "syscon";
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reg = <0x4140 0x18>;
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#clock-cells = <1>;
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};
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};
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dwc3_0: dwc3@4000000 {
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@@ -746,4 +757,97 @@ csi2_0: port@0 {
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};
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};
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};
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dss: dss@04a00000 {
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compatible = "ti,am65x-dss";
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reg = <0x0 0x04a00000 0x0 0x1000>, /* common */
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<0x0 0x04a02000 0x0 0x1000>, /* vidl1 */
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<0x0 0x04a06000 0x0 0x1000>, /* vid */
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<0x0 0x04a07000 0x0 0x1000>, /* ovr1 */
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<0x0 0x04a08000 0x0 0x1000>, /* ovr2 */
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<0x0 0x04a0a000 0x0 0x1000>, /* vp1 */
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<0x0 0x04a0b000 0x0 0x1000>; /* vp2 */
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reg-names = "common", "vidl1", "vid",
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"ovr1", "ovr2", "vp1", "vp2";
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ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>;
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power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 67 1>,
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<&k3_clks 216 1>,
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<&k3_clks 67 2>;
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clock-names = "fck", "vp1", "vp2";
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/*
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* Set vp2 clk (DPI_1_IN_CLK) mux to PLL4 via
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* DIV1. See "Figure 12-3365. DSS Integration"
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* in AM65x TRM for details.
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*/
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assigned-clocks = <&k3_clks 67 2>;
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assigned-clock-parents = <&k3_clks 67 5>;
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interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>;
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status = "disabled";
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dss_ports: ports {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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ehrpwm0: pwm@3000000 {
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compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
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#pwm-cells = <3>;
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reg = <0x0 0x3000000 0x0 0x100>;
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power-domains = <&k3_pds 40 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&ehrpwm_tbclk 0>, <&k3_clks 40 0>;
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clock-names = "tbclk", "fck";
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};
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ehrpwm1: pwm@3010000 {
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compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
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#pwm-cells = <3>;
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reg = <0x0 0x3010000 0x0 0x100>;
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power-domains = <&k3_pds 41 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&ehrpwm_tbclk 1>, <&k3_clks 41 0>;
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clock-names = "tbclk", "fck";
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};
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ehrpwm2: pwm@3020000 {
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compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
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#pwm-cells = <3>;
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reg = <0x0 0x3020000 0x0 0x100>;
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power-domains = <&k3_pds 42 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&ehrpwm_tbclk 2>, <&k3_clks 42 0>;
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clock-names = "tbclk", "fck";
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};
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ehrpwm3: pwm@3030000 {
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compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
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#pwm-cells = <3>;
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reg = <0x0 0x3030000 0x0 0x100>;
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power-domains = <&k3_pds 43 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&ehrpwm_tbclk 3>, <&k3_clks 43 0>;
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clock-names = "tbclk", "fck";
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};
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ehrpwm4: pwm@3040000 {
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compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
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#pwm-cells = <3>;
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reg = <0x0 0x3040000 0x0 0x100>;
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power-domains = <&k3_pds 44 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&ehrpwm_tbclk 4>, <&k3_clks 44 0>;
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clock-names = "tbclk", "fck";
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};
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ehrpwm5: pwm@3050000 {
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compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
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#pwm-cells = <3>;
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reg = <0x0 0x3050000 0x0 0x100>;
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power-domains = <&k3_pds 45 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&ehrpwm_tbclk 5>, <&k3_clks 45 0>;
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clock-names = "tbclk", "fck";
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};
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};
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@@ -89,4 +89,15 @@ wkup_gpio0: wkup_gpio0@42110000 {
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clocks = <&k3_clks 59 0>;
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clock-names = "gpio";
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};
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wkup_vtm0: thermal@42050000 {
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compatible = "ti,am654-vtm";
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reg = <0x42050000 0x25c>;
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power-domains = <&k3_pds 80 TI_SCI_PD_EXCLUSIVE>;
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#thermal-sensor-cells = <1>;
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};
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thermal_zones: thermal-zones {
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#include "k3-am654-industrial-thermal.dtsi"
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};
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};
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45
arch/arm64/boot/dts/ti/k3-am654-industrial-thermal.dtsi
Normal file
45
arch/arm64/boot/dts/ti/k3-am654-industrial-thermal.dtsi
Normal file
@@ -0,0 +1,45 @@
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// SPDX-License-Identifier: GPL-2.0
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#include <dt-bindings/thermal/thermal.h>
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mpu0_thermal: mpu0_thermal {
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polling-delay-passive = <250>; /* milliseconds */
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polling-delay = <500>; /* milliseconds */
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thermal-sensors = <&wkup_vtm0 0>;
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trips {
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mpu0_crit: mpu0_crit {
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temperature = <125000>; /* milliCelsius */
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hysteresis = <2000>; /* milliCelsius */
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type = "critical";
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};
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};
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};
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mpu1_thermal: mpu1_thermal {
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polling-delay-passive = <250>; /* milliseconds */
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polling-delay = <500>; /* milliseconds */
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thermal-sensors = <&wkup_vtm0 1>;
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trips {
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mpu1_crit: mpu1_crit {
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temperature = <125000>; /* milliCelsius */
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hysteresis = <2000>; /* milliCelsius */
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type = "critical";
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};
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};
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};
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mcu_thermal: mcu_thermal {
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polling-delay-passive = <250>; /* milliseconds */
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polling-delay = <500>; /* milliseconds */
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thermal-sensors = <&wkup_vtm0 2>;
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trips {
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mcu_crit: mcu_crit {
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temperature = <125000>; /* milliCelsius */
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hysteresis = <2000>; /* milliCelsius */
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type = "critical";
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};
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};
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};
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@@ -472,3 +472,23 @@ &cpsw_port1 {
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phy-mode = "rgmii-rxid";
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phy-handle = <&phy0>;
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};
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&dss {
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/*
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* These clock assignments are chosen to enable the following outputs:
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*
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* VP0 - DisplayPort SST
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* VP1 - DPI0
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* VP2 - DSI
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* VP3 - DPI1
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*/
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assigned-clocks = <&k3_clks 152 1>,
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<&k3_clks 152 4>,
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<&k3_clks 152 9>,
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<&k3_clks 152 13>;
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assigned-clock-parents = <&k3_clks 152 2>, /* PLL16_HSDIV0 */
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<&k3_clks 152 6>, /* PLL19_HSDIV0 */
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<&k3_clks 152 11>, /* PLL18_HSDIV0 */
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<&k3_clks 152 18>; /* PLL23_HSDIV0 */
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};
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@@ -736,6 +736,63 @@ ufs@4e84000 {
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};
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};
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dss: dss@04a00000 {
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compatible = "ti,j721e-dss";
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reg =
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<0x00 0x04a00000 0x00 0x10000>, /* common_m */
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<0x00 0x04a10000 0x00 0x10000>, /* common_s0*/
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<0x00 0x04b00000 0x00 0x10000>, /* common_s1*/
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<0x00 0x04b10000 0x00 0x10000>, /* common_s2*/
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<0x00 0x04a20000 0x00 0x10000>, /* vidl1 */
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<0x00 0x04a30000 0x00 0x10000>, /* vidl2 */
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<0x00 0x04a50000 0x00 0x10000>, /* vid1 */
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<0x00 0x04a60000 0x00 0x10000>, /* vid2 */
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<0x00 0x04a70000 0x00 0x10000>, /* ovr1 */
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<0x00 0x04a90000 0x00 0x10000>, /* ovr2 */
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<0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */
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<0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */
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<0x00 0x04a80000 0x00 0x10000>, /* vp1 */
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<0x00 0x04aa0000 0x00 0x10000>, /* vp2 */
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<0x00 0x04ac0000 0x00 0x10000>, /* vp3 */
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<0x00 0x04ae0000 0x00 0x10000>, /* vp4 */
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<0x00 0x04af0000 0x00 0x10000>; /* wb */
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reg-names = "common_m", "common_s0",
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"common_s1", "common_s2",
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"vidl1", "vidl2","vid1","vid2",
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"ovr1", "ovr2", "ovr3", "ovr4",
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"vp1", "vp2", "vp3", "vp4",
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"wb";
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clocks = <&k3_clks 152 0>,
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<&k3_clks 152 1>,
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<&k3_clks 152 4>,
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<&k3_clks 152 9>,
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<&k3_clks 152 13>;
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clock-names = "fck", "vp1", "vp2", "vp3", "vp4";
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power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
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interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "common_m",
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"common_s0",
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"common_s1",
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"common_s2";
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status = "disabled";
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dss_ports: ports {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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mcasp0: mcasp@2b00000 {
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compatible = "ti,am33xx-mcasp-audio";
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reg = <0x0 0x02b00000 0x0 0x2000>,
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@@ -963,4 +1020,22 @@ mcasp11: mcasp@2bb0000 {
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status = "disabled";
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};
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watchdog0: watchdog@2200000 {
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compatible = "ti,j7-rti-wdt";
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reg = <0x0 0x2200000 0x0 0x100>;
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clocks = <&k3_clks 252 1>;
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power-domains = <&k3_pds 252 TI_SCI_PD_EXCLUSIVE>;
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assigned-clocks = <&k3_clks 252 1>;
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assigned-clock-parents = <&k3_clks 252 5>;
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};
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watchdog1: watchdog@2210000 {
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compatible = "ti,j7-rti-wdt";
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reg = <0x0 0x2210000 0x0 0x100>;
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clocks = <&k3_clks 253 1>;
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power-domains = <&k3_pds 253 TI_SCI_PD_EXCLUSIVE>;
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assigned-clocks = <&k3_clks 253 1>;
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assigned-clock-parents = <&k3_clks 253 5>;
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};
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};
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