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drm/i915: Fail if DSC compression requirement is less than platform supports

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Currently we just clamp that value to the highest supported one, however that
means, we are not able to fit this into our available bandwidth range, so we
might see glitches or FIFO underruns.
While choosing less compressed bpp than min bpp required to handle the mode is
harmless and might even save some bandwidth, choosing higher compressed bpp than
min bpp required to handle the required mode config, can cause issues.
So in that case lets just conclude that even with DSC, we are not able to comply
with bandwidth requirements and fail.

v2: - s/clamp_t/min_t/ (Luca Coelho)

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Reviewed-by: Luca Coelho <luciano.coelho@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230629122534.8815-1-stanislav.lisovskiy@intel.com
This commit is contained in:
Stanislav Lisovskiy
2023-06-29 15:25:34 +03:00
parent ce98870593
commit a122243367
1 changed files with 11 additions and 2 deletions
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13
drivers/gpu/drm/i915/display/intel_dp.c
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@@ -713,9 +713,18 @@ u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 p
/*
* According to BSpec, 27 is the max DSC output bpp,
* 8 is the min DSC output bpp
* 8 is the min DSC output bpp.
* While we can still clamp higher bpp values to 27, saving bandwidth,
* if it is required to oompress up to bpp < 8, means we can't do
* that and probably means we can't fit the required mode, even with
* DSC enabled.
*/
bits_per_pixel = clamp_t(u32, bits_per_pixel, 8, 27);
if (bits_per_pixel < 8) {
drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min 8\n",
bits_per_pixel);
return 0;
}
bits_per_pixel = min_t(u32, bits_per_pixel, 27);
} else {
/* Find the nearest match in the array of known BPPs from VESA */
for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) {