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ARM: dts: stm32: stm32mp15x-mecio1-io: Move expander gpio-line-names to board files

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Move the gpio-line-names properties for the I2C GPIO expanders (gpio0
and gpio1) out of the common mecio1-io.dtsi file and into the specific
board dts files.

The layout originally defined in the common include file belonged to the
mecio1r1 (Revision 1) hardware. This layout is moved 1:1 into the
stm32mp153c-mecio1r1.dts file.

The mecio1r0 (Revision 0) hardware utilizes a completely different
pinout for these expanders. A new, accurate mapping reflecting the
Revision 0 schematics is added to stm32mp151c-mecio1r0.dts.

Fixes: 8267753c89 ("ARM: dts: stm32: Add MECIO1 and MECT1S board variants")
Co-developed-by: Oleksij Rempel <o.rempel@pengutronix.de>
Signed-off-by: David Jander <david@protonic.nl>
Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/20260318105123.819807-8-o.rempel@pengutronix.de
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
This commit is contained in:
David Jander
2026-03-18 11:51:23 +01:00
committed by Alexandre Torgue
parent dfb93c4acc
commit a0d6c2a06f
3 changed files with 28 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
arch/arm/boot/dts/st/stm32mp151c-mecio1r0.dts
View File

@@ -97,6 +97,20 @@ &ethernet0 {
st,eth-clk-sel;
};
&gpio0 {
gpio-line-names = "HSIN0_BIAS", "HSIN1_BIAS", "HSIN2_BIAS", "HSIN3_BIAS",
"HSIN4_BIAS", "", "STP_VREF0_LVL", "HSIN_VREF0_LVL",
"STP0_FB_BIAS", "STP1_FB_BIAS", "STP2_FB_BIAS", "STP3_FB_BIAS",
"", "", "", "";
};
&gpio1 {
gpio-line-names = "HSIN5_BIAS", "HSIN6_BIAS", "HSIN7_BIAS", "HSIN8_BIAS",
"HSIN9_BIAS", "", "STP_VREF1_LVL", "HSIN_VREF1_LVL",
"STP4_FB_BIAS", "STP5_FB_BIAS", "STP6_FB_BIAS", "",
"", "", "LSIN8_BIAS", "LSIN9_BIAS";
};
&gpiod {
gpio-line-names = "", "", "", "",
"", "", "", "",

14
arch/arm/boot/dts/st/stm32mp153c-mecio1r1.dts
View File

@@ -90,6 +90,20 @@ &clk_hse {
clock-frequency = <24000000>;
};
&gpio0 {
gpio-line-names = "HSIN0_BIAS", "HSIN1_BIAS", "HSIN2_BIAS", "HSIN3_BIAS",
"", "", "HSIN_VREF0_LVL", "HSIN_VREF1_LVL",
"HSIN4_BIAS", "HSIN5_BIAS", "HSIN6_BIAS", "HSIN7_BIAS",
"", "", "", "";
};
&gpio1 {
gpio-line-names = "HSIN8_BIAS", "HSIN9_BIAS", "HSIN10_BIAS", "HSIN11_BIAS",
"", "", "HSIN_VREF2_LVL", "HSIN_VREF3_LVL",
"HSIN12_BIAS", "HSIN13_BIAS", "HSIN14_BIAS", "HSIN15_BIAS",
"", "", "LSIN8_BIAS", "LSIN9_BIAS";
};
&gpioa {
gpio-line-names = "", "", "", "",
"", "", "", "",

8
arch/arm/boot/dts/st/stm32mp15x-mecio1-io.dtsi
View File

@@ -184,10 +184,6 @@ gpio0: gpio@20 {
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names = "HSIN0_BIAS", "HSIN1_BIAS", "HSIN2_BIAS", "HSIN3_BIAS",
"", "", "HSIN_VREF0_LVL", "HSIN_VREF1_LVL",
"HSIN4_BIAS", "HSIN5_BIAS", "HSIN6_BIAS", "HSIN7_BIAS",
"", "", "", "";
};
gpio1: gpio@21 {
@@ -195,10 +191,6 @@ gpio1: gpio@21 {
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names = "HSIN8_BIAS", "HSIN9_BIAS", "HSIN10_BIAS", "HSIN11_BIAS",
"", "", "HSIN_VREF2_LVL", "HSIN_VREF3_LVL",
"HSIN12_BIAS", "HSIN13_BIAS", "HSIN14_BIAS", "HSIN15_BIAS",
"", "", "LSIN8_BIAS", "LSIN9_BIAS";
};
};