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Merge tag 'char-misc-6.15-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc

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Pull char/misc fixes from Greg KH:
 "Here are two counter driver fixes that I realized I never sent to you
  for 6.14-final.

  They have been in my for weeks, as well as linux-next, my fault for
  not sending them earlier. They are:

   - bugfix for stm32-lptimer-cnt counter driver

   - bugfix for microchip-tcb-capture counter driver

  Again, these have been in linux-next for weeks with no reported
  issues"

* tag 'char-misc-6.15-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc:
  counter: microchip-tcb-capture: Fix undefined counter channel state on probe
  counter: stm32-lptimer-cnt: fix error handling when enabling
This commit is contained in:
Linus Torvalds
2025-04-02 18:03:34 -07:00
parent 94d471a4f4 2dc2509321
commit a0935e4ca3
2 changed files with 34 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

19
drivers/counter/microchip-tcb-capture.c
View File

@@ -519,6 +519,25 @@ static int mchp_tc_probe(struct platform_device *pdev)
channel);
}
/* Disable Quadrature Decoder and position measure */
ret = regmap_update_bits(regmap, ATMEL_TC_BMR, ATMEL_TC_QDEN | ATMEL_TC_POSEN, 0);
if (ret)
return ret;
/* Setup the period capture mode */
ret = regmap_update_bits(regmap, ATMEL_TC_REG(priv->channel[0], CMR),
ATMEL_TC_WAVE | ATMEL_TC_ABETRG | ATMEL_TC_CMR_MASK |
ATMEL_TC_TCCLKS,
ATMEL_TC_CMR_MASK);
if (ret)
return ret;
/* Enable clock and trigger counter */
ret = regmap_write(regmap, ATMEL_TC_REG(priv->channel[0], CCR),
ATMEL_TC_CLKEN | ATMEL_TC_SWTRG);
if (ret)
return ret;
priv->tc_cfg = tcb_config;
priv->regmap = regmap;
counter->name = dev_name(&pdev->dev);

24
drivers/counter/stm32-lptimer-cnt.c
View File

@@ -58,37 +58,43 @@ static int stm32_lptim_set_enable_state(struct stm32_lptim_cnt *priv,
return 0;
}
ret = clk_enable(priv->clk);
if (ret)
goto disable_cnt;
/* LP timer must be enabled before writing CMP & ARR */
ret = regmap_write(priv->regmap, STM32_LPTIM_ARR, priv->ceiling);
if (ret)
return ret;
goto disable_clk;
ret = regmap_write(priv->regmap, STM32_LPTIM_CMP, 0);
if (ret)
return ret;
goto disable_clk;
/* ensure CMP & ARR registers are properly written */
ret = regmap_read_poll_timeout(priv->regmap, STM32_LPTIM_ISR, val,
(val & STM32_LPTIM_CMPOK_ARROK) == STM32_LPTIM_CMPOK_ARROK,
100, 1000);
if (ret)
return ret;
goto disable_clk;
ret = regmap_write(priv->regmap, STM32_LPTIM_ICR,
STM32_LPTIM_CMPOKCF_ARROKCF);
if (ret)
return ret;
goto disable_clk;
ret = clk_enable(priv->clk);
if (ret) {
regmap_write(priv->regmap, STM32_LPTIM_CR, 0);
return ret;
}
priv->enabled = true;
/* Start LP timer in continuous mode */
return regmap_update_bits(priv->regmap, STM32_LPTIM_CR,
STM32_LPTIM_CNTSTRT, STM32_LPTIM_CNTSTRT);
disable_clk:
clk_disable(priv->clk);
disable_cnt:
regmap_write(priv->regmap, STM32_LPTIM_CR, 0);
return ret;
}
static int stm32_lptim_setup(struct stm32_lptim_cnt *priv, int enable)