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drm/amdgpu: Replace HQD terminology with slots naming

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The term "HQD" is CP-specific and doesn't
accurately describe the queue resources for other IP blocks like SDMA,
VCN, or VPE. This change:

1. Renames `num_hqds` to `num_slots` in amdgpu_kms.c to better reflect
   the generic nature of the resource counting
2. Updates the UAPI struct member from `userq_num_hqds` to `userq_num_slots`
3. Maintains the same functionality while using more appropriate terminology

Signed-off-by: Jesse Zhang <Jesse.Zhang@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Jesse Zhang
2025-07-04 15:17:43 +08:00
committed by Alex Deucher
parent 78d0a27ae0
commit 9ffab039bc
2 changed files with 7 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
View File

@@ -399,7 +399,7 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
uint32_t ib_size_alignment = 0;
enum amd_ip_block_type type;
unsigned int num_rings = 0;
uint32_t num_hqds = 0;
uint32_t num_slots = 0;
unsigned int i, j;
if (info->query_hw_ip.ip_instance >= AMDGPU_HW_IP_INSTANCE_MAX_COUNT)
@@ -415,7 +415,7 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
if (!adev->gfx.disable_uq) {
for (i = 0; i < AMDGPU_MES_MAX_GFX_PIPES; i++)
num_hqds += hweight32(adev->mes.gfx_hqd_mask[i]);
num_slots += hweight32(adev->mes.gfx_hqd_mask[i]);
}
ib_start_alignment = 32;
@@ -430,7 +430,7 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
if (!adev->sdma.disable_uq) {
for (i = 0; i < AMDGPU_MES_MAX_COMPUTE_PIPES; i++)
num_hqds += hweight32(adev->mes.compute_hqd_mask[i]);
num_slots += hweight32(adev->mes.compute_hqd_mask[i]);
}
ib_start_alignment = 32;
@@ -445,7 +445,7 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
if (!adev->gfx.disable_uq) {
for (i = 0; i < AMDGPU_MES_MAX_SDMA_PIPES; i++)
num_hqds += hweight32(adev->mes.sdma_hqd_mask[i]);
num_slots += hweight32(adev->mes.sdma_hqd_mask[i]);
}
ib_start_alignment = 256;
@@ -589,7 +589,7 @@ static int amdgpu_hw_ip_info(struct amdgpu_device *adev,
}
result->capabilities_flags = 0;
result->available_rings = (1 << num_rings) - 1;
result->userq_num_hqds = num_hqds;
result->userq_num_slots = num_slots;
result->ib_start_alignment = ib_start_alignment;
result->ib_size_alignment = ib_size_alignment;
return 0;

4
include/uapi/drm/amdgpu_drm.h
View File

@@ -1493,8 +1493,8 @@ struct drm_amdgpu_info_hw_ip {
__u32 available_rings;
/** version info: bits 23:16 major, 15:8 minor, 7:0 revision */
__u32 ip_discovery_version;
/* Userq available hqds */
__u32 userq_num_hqds;
/* Userq available slots */
__u32 userq_num_slots;
};
/* GFX metadata BO sizes and alignment info (in bytes) */