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Merge tag 'amlogic-dt-2' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into next/dt

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Pull "Amlogic 32-bit DT updates for v4.15, round 2" from Kevin Hilman:
- enable new GPIO IRQ controller
- add efuse node

* tag 'amlogic-dt-2' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic:
  ARM: dts: meson: add the efuse node
  ARM: dts: meson8b: enable gpio interrupt controller
  ARM: dts: meson8b: add support for booting the secondary CPU cores
  ARM: dts: meson8: add support for booting the secondary CPU cores
This commit is contained in:
Arnd Bergmann
2017-10-30 14:11:46 +01:00
parent b3a8704446 2cb51a8ddd
commit 9f4fb2081b
4 changed files with 88 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

24
arch/arm/boot/dts/meson.dtsi
View File

@@ -85,6 +85,15 @@ assist: assist@7c00 {
reg = <0x7c00 0x200>;
};
gpio_intc: interrupt-controller@9880 {
compatible = "amlogic,meson-gpio-intc";
reg = <0xc1109880 0x10>;
interrupt-controller;
#interrupt-cells = <2>;
amlogic,channel-interrupts = <64 65 66 67 68 69 70 71>;
status = "disabled";
};
hwrng: rng@8100 {
compatible = "amlogic,meson-rng";
reg = <0x8100 0x8>;
@@ -271,5 +280,20 @@ bootrom: bootrom@d9040000 {
compatible = "amlogic,meson-mx-bootrom", "syscon";
reg = <0xd9040000 0x10000>;
};
secbus: secbus@da000000 {
compatible = "simple-bus";
reg = <0xda000000 0x6000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0x0 0xda000000 0x6000>;
efuse: nvmem@0 {
compatible = "amlogic,meson6-efuse";
reg = <0x0 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
};
};
};
}; /* end of / */

3
arch/arm/boot/dts/meson6.dtsi
View File

@@ -84,6 +84,9 @@ clk81: clk@0 {
};
}; /* end of / */
&efuse {
status = "disabled";
};
&uart_AO {
clocks = <&xtal>, <&clk81>, <&clk81>;

27
arch/arm/boot/dts/meson8.dtsi
View File

@@ -45,6 +45,7 @@
#include <dt-bindings/clock/meson8b-clkc.h>
#include <dt-bindings/gpio/meson8-gpio.h>
#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
#include "meson.dtsi"
/ {
@@ -60,6 +61,8 @@ cpu@200 {
compatible = "arm,cortex-a9";
next-level-cache = <&L2>;
reg = <0x200>;
enable-method = "amlogic,meson8-smp";
resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
};
cpu@201 {
@@ -67,6 +70,8 @@ cpu@201 {
compatible = "arm,cortex-a9";
next-level-cache = <&L2>;
reg = <0x201>;
enable-method = "amlogic,meson8-smp";
resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
};
cpu@202 {
@@ -74,6 +79,8 @@ cpu@202 {
compatible = "arm,cortex-a9";
next-level-cache = <&L2>;
reg = <0x202>;
enable-method = "amlogic,meson8-smp";
resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
};
cpu@203 {
@@ -81,6 +88,8 @@ cpu@203 {
compatible = "arm,cortex-a9";
next-level-cache = <&L2>;
reg = <0x203>;
enable-method = "amlogic,meson8-smp";
resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>;
};
};
@@ -118,6 +127,11 @@ scu@c4300000 {
}; /* end of / */
&aobus {
pmu: pmu@e0 {
compatible = "amlogic,meson8-pmu", "syscon";
reg = <0xe0 0x8>;
};
pinctrl_aobus: pinctrl@84 {
compatible = "amlogic,meson8-aobus-pinctrl";
reg = <0x84 0xc>;
@@ -254,6 +268,19 @@ mux {
};
};
&ahb_sram {
smp-sram@1ff80 {
compatible = "amlogic,meson8-smp-sram";
reg = <0x1ff80 0x8>;
};
};
&efuse {
compatible = "amlogic,meson8-efuse";
clocks = <&clkc CLKID_EFUSE>;
clock-names = "core";
};
&ethmac {
clocks = <&clkc CLKID_ETH>;
clock-names = "stmmaceth";

34
arch/arm/boot/dts/meson8b.dtsi
View File

@@ -47,6 +47,7 @@
#include <dt-bindings/clock/meson8b-clkc.h>
#include <dt-bindings/gpio/meson8b-gpio.h>
#include <dt-bindings/reset/amlogic,meson8b-reset.h>
#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
#include "meson.dtsi"
/ {
@@ -59,6 +60,8 @@ cpu@200 {
compatible = "arm,cortex-a5";
next-level-cache = <&L2>;
reg = <0x200>;
enable-method = "amlogic,meson8b-smp";
resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
};
cpu@201 {
@@ -66,6 +69,8 @@ cpu@201 {
compatible = "arm,cortex-a5";
next-level-cache = <&L2>;
reg = <0x201>;
enable-method = "amlogic,meson8b-smp";
resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
};
cpu@202 {
@@ -73,6 +78,8 @@ cpu@202 {
compatible = "arm,cortex-a5";
next-level-cache = <&L2>;
reg = <0x202>;
enable-method = "amlogic,meson8b-smp";
resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
};
cpu@203 {
@@ -80,6 +87,8 @@ cpu@203 {
compatible = "arm,cortex-a5";
next-level-cache = <&L2>;
reg = <0x203>;
enable-method = "amlogic,meson8b-smp";
resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>;
};
};
@@ -102,6 +111,11 @@ scu@c4300000 {
}; /* end of / */
&aobus {
pmu: pmu@e0 {
compatible = "amlogic,meson8b-pmu", "syscon";
reg = <0xe0 0x18>;
};
pinctrl_aobus: pinctrl@84 {
compatible = "amlogic,meson8b-aobus-pinctrl";
reg = <0x84 0xc>;
@@ -174,11 +188,31 @@ gpio: banks@80b0 {
};
};
&ahb_sram {
smp-sram@1ff80 {
compatible = "amlogic,meson8b-smp-sram";
reg = <0x1ff80 0x8>;
};
};
&efuse {
compatible = "amlogic,meson8b-efuse";
clocks = <&clkc CLKID_EFUSE>;
clock-names = "core";
};
&ethmac {
clocks = <&clkc CLKID_ETH>;
clock-names = "stmmaceth";
};
&gpio_intc {
compatible = "amlogic,meson-gpio-intc",
"amlogic,meson8b-gpio-intc";
status = "okay";
};
&hwrng {
compatible = "amlogic,meson8b-rng", "amlogic,meson-rng";
clocks = <&clkc CLKID_RNG0>;