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Merge tag 'omap-for-v5.16/gpmc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/dt

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Changes for omap gpmc bindings and devicetree files for v5.16

A series of changes to update the gpmc related bindings to yaml
format, and a few non-urgent dts fixes.

* tag 'omap-for-v5.16/gpmc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: dts: omap: fix gpmc,mux-add-data type
  ARM: dts: omap: Fix boolean properties gpmc,cycle2cycle-{same|diff}csen
  dt-bindings: memory-controllers: ti,gpmc: Convert to yaml
  dt-bindings: mtd: ti,gpmc-onenand: Convert to yaml
  dt-bindings: mtd: ti,gpmc-nand: Convert to yaml
  dt-bindings: memory-controllers: Introduce ti,gpmc-child
  dt-bindings: net: Remove gpmc-eth.txt
  dt-bindings: mtd: Remove gpmc-nor.txt

Link: https://lore.kernel.org/r/pull-1634280279-284035@atomide.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2021-10-20 23:18:00 +02:00
parent 06fab4a544 51b9e22ffd
commit 9f2feb32c2
16 changed files with 631 additions and 559 deletions
Download Patch File Download Diff File Expand all files Collapse all files

157
Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
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Device tree bindings for OMAP general purpose memory controllers (GPMC)
The actual devices are instantiated from the child nodes of a GPMC node.
Required properties:
- compatible: Should be set to one of the following:
ti,omap2420-gpmc (omap2420)
ti,omap2430-gpmc (omap2430)
ti,omap3430-gpmc (omap3430 & omap3630)
ti,omap4430-gpmc (omap4430 & omap4460 & omap543x)
ti,am3352-gpmc (am335x devices)
- reg: A resource specifier for the register space
(see the example below)
- ti,hwmods: Should be set to "ti,gpmc" until the DT transition is
completed.
- #address-cells: Must be set to 2 to allow memory address translation
- #size-cells: Must be set to 1 to allow CS address passing
- gpmc,num-cs: The maximum number of chip-select lines that controller
can support.
- gpmc,num-waitpins: The maximum number of wait pins that controller can
support.
- ranges: Must be set up to reflect the memory layout with four
integer values for each chip-select line in use:
<cs-number> 0 <physical address of mapping> <size>
Currently, calculated values derived from the contents
of the per-CS register GPMC_CONFIG7 (as set up by the
bootloader) are used for the physical address decoding.
As this will change in the future, filling correct
values here is a requirement.
- interrupt-controller: The GPMC driver implements and interrupt controller for
the NAND events "fifoevent" and "termcount" plus the
rising/falling edges on the GPMC_WAIT pins.
The interrupt number mapping is as follows
0 - NAND_fifoevent
1 - NAND_termcount
2 - GPMC_WAIT0 pin edge
3 - GPMC_WAIT1 pin edge, and so on.
- interrupt-cells: Must be set to 2
- gpio-controller: The GPMC driver implements a GPIO controller for the
GPMC WAIT pins that can be used as general purpose inputs.
0 maps to GPMC_WAIT0 pin.
- gpio-cells: Must be set to 2
Required properties when using NAND prefetch dma:
- dmas GPMC NAND prefetch dma channel
- dma-names Must be set to "rxtx"
Timing properties for child nodes. All are optional and default to 0.
- gpmc,sync-clk-ps: Minimum clock period for synchronous mode, in picoseconds
Chip-select signal timings (in nanoseconds) corresponding to GPMC_CONFIG2:
- gpmc,cs-on-ns: Assertion time
- gpmc,cs-rd-off-ns: Read deassertion time
- gpmc,cs-wr-off-ns: Write deassertion time
ADV signal timings (in nanoseconds) corresponding to GPMC_CONFIG3:
- gpmc,adv-on-ns: Assertion time
- gpmc,adv-rd-off-ns: Read deassertion time
- gpmc,adv-wr-off-ns: Write deassertion time
- gpmc,adv-aad-mux-on-ns: Assertion time for AAD
- gpmc,adv-aad-mux-rd-off-ns: Read deassertion time for AAD
- gpmc,adv-aad-mux-wr-off-ns: Write deassertion time for AAD
WE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4:
- gpmc,we-on-ns Assertion time
- gpmc,we-off-ns: Deassertion time
OE signals timings (in nanoseconds) corresponding to GPMC_CONFIG4:
- gpmc,oe-on-ns: Assertion time
- gpmc,oe-off-ns: Deassertion time
- gpmc,oe-aad-mux-on-ns: Assertion time for AAD
- gpmc,oe-aad-mux-off-ns: Deassertion time for AAD
Access time and cycle time timings (in nanoseconds) corresponding to
GPMC_CONFIG5:
- gpmc,page-burst-access-ns: Multiple access word delay
- gpmc,access-ns: Start-cycle to first data valid delay
- gpmc,rd-cycle-ns: Total read cycle time
- gpmc,wr-cycle-ns: Total write cycle time
- gpmc,bus-turnaround-ns: Turn-around time between successive accesses
- gpmc,cycle2cycle-delay-ns: Delay between chip-select pulses
- gpmc,clk-activation-ns: GPMC clock activation time
- gpmc,wait-monitoring-ns: Start of wait monitoring with regard to valid
data
Boolean timing parameters. If property is present parameter enabled and
disabled if omitted:
- gpmc,adv-extra-delay: ADV signal is delayed by half GPMC clock
- gpmc,cs-extra-delay: CS signal is delayed by half GPMC clock
- gpmc,cycle2cycle-diffcsen: Add "cycle2cycle-delay" between successive
accesses to a different CS
- gpmc,cycle2cycle-samecsen: Add "cycle2cycle-delay" between successive
accesses to the same CS
- gpmc,oe-extra-delay: OE signal is delayed by half GPMC clock
- gpmc,we-extra-delay: WE signal is delayed by half GPMC clock
- gpmc,time-para-granularity: Multiply all access times by 2
The following are only applicable to OMAP3+ and AM335x:
- gpmc,wr-access-ns: In synchronous write mode, for single or
burst accesses, defines the number of
GPMC_FCLK cycles from start access time
to the GPMC_CLK rising edge used by the
memory device for the first data capture.
- gpmc,wr-data-mux-bus-ns: In address-data multiplex mode, specifies
the time when the first data is driven on
the address-data bus.
GPMC chip-select settings properties for child nodes. All are optional.
- gpmc,burst-length Page/burst length. Must be 4, 8 or 16.
- gpmc,burst-wrap Enables wrap bursting
- gpmc,burst-read Enables read page/burst mode
- gpmc,burst-write Enables write page/burst mode
- gpmc,device-width Total width of device(s) connected to a GPMC
chip-select in bytes. The GPMC supports 8-bit
and 16-bit devices and so this property must be
1 or 2.
- gpmc,mux-add-data Address and data multiplexing configuration.
Valid values are 1 for address-address-data
multiplexing mode and 2 for address-data
multiplexing mode.
- gpmc,sync-read Enables synchronous read. Defaults to asynchronous
is this is not set.
- gpmc,sync-write Enables synchronous writes. Defaults to asynchronous
is this is not set.
- gpmc,wait-pin Wait-pin used by client. Must be less than
"gpmc,num-waitpins".
- gpmc,wait-on-read Enables wait monitoring on reads.
- gpmc,wait-on-write Enables wait monitoring on writes.
Example for an AM33xx board:
gpmc: gpmc@50000000 {
compatible = "ti,am3352-gpmc";
ti,hwmods = "gpmc";
reg = <0x50000000 0x2000>;
interrupts = <100>;
dmas = <&edma 52 0>;
dma-names = "rxtx";
gpmc,num-cs = <8>;
gpmc,num-waitpins = <2>;
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0x08000000 0x10000000>; /* CS0 @addr 0x8000000, size 0x10000000 */
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
/* child nodes go here */
};

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/ti,gpmc-child.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: device tree bindings for children of the Texas Instruments GPMC
maintainers:
- Tony Lindgren <tony@atomide.com>
- Roger Quadros <rogerq@kernel.org>
description:
This binding is meant for the child nodes of the GPMC node. The node
represents any device connected to the GPMC bus. It may be a Flash chip,
RAM chip or Ethernet controller, etc. These properties are meant for
configuring the GPMC settings/timings and will accompany the bindings
supported by the respective device.
properties:
reg: true
# GPMC Timing properties for child nodes. All are optional and default to 0.
gpmc,sync-clk-ps:
description: Minimum clock period for synchronous mode
default: 0
# Chip-select signal timings corresponding to GPMC_CONFIG2:
gpmc,cs-on-ns:
description: Assertion time
default: 0
gpmc,cs-rd-off-ns:
description: Read deassertion time
default: 0
gpmc,cs-wr-off-ns:
description: Write deassertion time
default: 0
# ADV signal timings corresponding to GPMC_CONFIG3:
gpmc,adv-on-ns:
description: Assertion time
default: 0
gpmc,adv-rd-off-ns:
description: Read deassertion time
default: 0
gpmc,adv-wr-off-ns:
description: Write deassertion time
default: 0
gpmc,adv-aad-mux-on-ns:
description: Assertion time for AAD
default: 0
gpmc,adv-aad-mux-rd-off-ns:
description: Read deassertion time for AAD
default: 0
gpmc,adv-aad-mux-wr-off-ns:
description: Write deassertion time for AAD
default: 0
# WE signals timings corresponding to GPMC_CONFIG4:
gpmc,we-on-ns:
description: Assertion time
default: 0
gpmc,we-off-ns:
description: Deassertion time
default: 0
# OE signals timings corresponding to GPMC_CONFIG4:
gpmc,oe-on-ns:
description: Assertion time
default: 0
gpmc,oe-off-ns:
description: Deassertion time
default: 0
gpmc,oe-aad-mux-on-ns:
description: Assertion time for AAD
default: 0
gpmc,oe-aad-mux-off-ns:
description: Deassertion time for AAD
default: 0
# Access time and cycle time timings (in nanoseconds) corresponding to
# GPMC_CONFIG5:
gpmc,page-burst-access-ns:
description: Multiple access word delay
default: 0
gpmc,access-ns:
description: Start-cycle to first data valid delay
default: 0
gpmc,rd-cycle-ns:
description: Total read cycle time
default: 0
gpmc,wr-cycle-ns:
description: Total write cycle time
default: 0
gpmc,bus-turnaround-ns:
description: Turn-around time between successive accesses
default: 0
gpmc,cycle2cycle-delay-ns:
description: Delay between chip-select pulses
default: 0
gpmc,clk-activation-ns:
description: GPMC clock activation time
default: 0
gpmc,wait-monitoring-ns:
description: Start of wait monitoring with regard to valid data
default: 0
# Boolean timing parameters. If property is present, parameter is enabled
# otherwise disabled.
gpmc,adv-extra-delay:
description: ADV signal is delayed by half GPMC clock
type: boolean
gpmc,cs-extra-delay:
description: CS signal is delayed by half GPMC clock
type: boolean
gpmc,cycle2cycle-diffcsen:
description: |
Add "cycle2cycle-delay" between successive accesses
to a different CS
type: boolean
gpmc,cycle2cycle-samecsen:
description: |
Add "cycle2cycle-delay" between successive accesses
to the same CS
type: boolean
gpmc,oe-extra-delay:
description: OE signal is delayed by half GPMC clock
type: boolean
gpmc,we-extra-delay:
description: WE signal is delayed by half GPMC clock
type: boolean
gpmc,time-para-granularity:
description: Multiply all access times by 2
type: boolean
# The following two properties are applicable only to OMAP3+ and AM335x:
gpmc,wr-access-ns:
description: |
In synchronous write mode, for single or
burst accesses, defines the number of
GPMC_FCLK cycles from start access time
to the GPMC_CLK rising edge used by the
memory device for the first data capture.
default: 0
gpmc,wr-data-mux-bus-ns:
description: |
In address-data multiplex mode, specifies
the time when the first data is driven on
the address-data bus.
default: 0
# GPMC chip-select settings properties for child nodes. All are optional.
gpmc,burst-length:
description: Page/burst length.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 4, 8, 16]
default: 0
gpmc,burst-wrap:
description: Enables wrap bursting
type: boolean
gpmc,burst-read:
description: Enables read page/burst mode
type: boolean
gpmc,burst-write:
description: Enables write page/burst mode
type: boolean
gpmc,device-width:
description: |
Total width of device(s) connected to a GPMC
chip-select in bytes. The GPMC supports 8-bit
and 16-bit devices and so this property must be
1 or 2.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [1, 2]
default: 1
gpmc,mux-add-data:
description: |
Address and data multiplexing configuration.
Valid values are
0 for Non multiplexed mode
1 for address-address-data multiplexing mode and
2 for address-data multiplexing mode.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2]
gpmc,sync-read:
description: |
Enables synchronous read. Defaults to asynchronous
is this is not set.
type: boolean
gpmc,sync-write:
description: |
Enables synchronous writes. Defaults to asynchronous
is this is not set.
type: boolean
gpmc,wait-pin:
description: |
Wait-pin used by client. Must be less than "gpmc,num-waitpins".
$ref: /schemas/types.yaml#/definitions/uint32
gpmc,wait-on-read:
description: Enables wait monitoring on reads.
type: boolean
gpmc,wait-on-write:
description: Enables wait monitoring on writes.
type: boolean
required:
- reg
# the GPMC child will have its own native properties
additionalProperties: true

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/ti,gpmc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Texas Instruments GPMC Memory Controller device-tree bindings
maintainers:
- Tony Lindgren <tony@atomide.com>
- Roger Quadros <rogerq@kernel.org>
description:
The GPMC is a unified memory controller dedicated for interfacing
with external memory devices like
- Asynchronous SRAM-like memories and ASICs
- Asynchronous, synchronous, and page mode burst NOR flash
- NAND flash
- Pseudo-SRAM devices
properties:
compatible:
items:
- enum:
- ti,am3352-gpmc
- ti,omap2420-gpmc
- ti,omap2430-gpmc
- ti,omap3430-gpmc
- ti,omap4430-gpmc
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
description: |
Functional clock. Used for bus timing calculations and
GPMC configuration.
clock-names:
items:
- const: fck
dmas:
items:
- description: DMA channel for GPMC NAND prefetch
dma-names:
items:
- const: rxtx
"#address-cells": true
"#size-cells": true
gpmc,num-cs:
description: maximum number of supported chip-select lines.
$ref: /schemas/types.yaml#/definitions/uint32
gpmc,num-waitpins:
description: maximum number of supported wait pins.
$ref: /schemas/types.yaml#/definitions/uint32
ranges:
minItems: 1
description: |
Must be set up to reflect the memory layout with four
integer values for each chip-select line in use,
<cs-number> 0 <physical address of mapping> <size>
items:
- description: NAND bank 0
- description: NOR/SRAM bank 0
- description: NOR/SRAM bank 1
'#interrupt-cells':
const: 2
interrupt-controller:
description: |
The GPMC driver implements and interrupt controller for
the NAND events "fifoevent" and "termcount" plus the
rising/falling edges on the GPMC_WAIT pins.
The interrupt number mapping is as follows
0 - NAND_fifoevent
1 - NAND_termcount
2 - GPMC_WAIT0 pin edge
3 - GPMC_WAIT1 pin edge, and so on.
'#gpio-cells':
const: 2
gpio-controller:
description: |
The GPMC driver implements a GPIO controller for the
GPMC WAIT pins that can be used as general purpose inputs.
0 maps to GPMC_WAIT0 pin.
ti,hwmods:
description:
Name of the HWMOD associated with GPMC. This is for legacy
omap2/3 platforms only.
$ref: /schemas/types.yaml#/definitions/string
deprecated: true
ti,no-idle-on-init:
description:
Prevent idling the module at init. This is for legacy omap2/3
platforms only.
type: boolean
deprecated: true
patternProperties:
"@[0-7],[a-f0-9]+$":
type: object
description: |
The child device node represents the device connected to the GPMC
bus. The device can be a NAND chip, SRAM device, NOR device
or an ASIC.
allOf:
- $ref: "ti,gpmc-child.yaml"
unevaluatedProperties: false
required:
- compatible
- reg
- gpmc,num-cs
- gpmc,num-waitpins
- "#address-cells"
- "#size-cells"
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
gpmc: memory-controller@50000000 {
compatible = "ti,am3352-gpmc";
reg = <0x50000000 0x2000>;
interrupts = <100>;
clocks = <&l3s_clkctrl>;
clock-names = "fck";
dmas = <&edma 52 0>;
dma-names = "rxtx";
gpmc,num-cs = <8>;
gpmc,num-waitpins = <2>;
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0x08000000 0x10000000>; /* CS0 @addr 0x8000000, size 0x10000000 */
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
nand@0,0 {
compatible = "ti,omap2-nand";
reg = <0 0 4>;
interrupt-parent = <&gpmc>;
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
ti,nand-xfer-type = "prefetch-dma";
ti,nand-ecc-opt = "bch16";
ti,elm-id = <&elm>;
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 pin */
};
};

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Device tree bindings for GPMC connected NANDs
GPMC connected NAND (found on OMAP boards) are represented as child nodes of
the GPMC controller with a name of "nand".
All timing relevant properties as well as generic gpmc child properties are
explained in a separate documents - please refer to
Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
For NAND specific properties such as ECC modes or bus width, please refer to
Documentation/devicetree/bindings/mtd/nand-controller.yaml
Required properties:
- compatible: "ti,omap2-nand"
- reg: range id (CS number), base offset and length of the
NAND I/O space
- interrupts: Two interrupt specifiers, one for fifoevent, one for termcount.
Optional properties:
- nand-bus-width: Set this numeric value to 16 if the hardware
is wired that way. If not specified, a bus
width of 8 is assumed.
- ti,nand-ecc-opt: A string setting the ECC layout to use. One of:
"sw" 1-bit Hamming ecc code via software
"hw" <deprecated> use "ham1" instead
"hw-romcode" <deprecated> use "ham1" instead
"ham1" 1-bit Hamming ecc code
"bch4" 4-bit BCH ecc code
"bch8" 8-bit BCH ecc code
"bch16" 16-bit BCH ECC code
Refer below "How to select correct ECC scheme for your device ?"
- ti,nand-xfer-type: A string setting the data transfer type. One of:
"prefetch-polled" Prefetch polled mode (default)
"polled" Polled mode, without prefetch
"prefetch-dma" Prefetch enabled DMA mode
"prefetch-irq" Prefetch enabled irq mode
- elm_id: <deprecated> use "ti,elm-id" instead
- ti,elm-id: Specifies phandle of the ELM devicetree node.
ELM is an on-chip hardware engine on TI SoC which is used for
locating ECC errors for BCHx algorithms. SoC devices which have
ELM hardware engines should specify this device node in .dtsi
Using ELM for ECC error correction frees some CPU cycles.
- rb-gpios: GPIO specifier for the ready/busy# pin.
For inline partition table parsing (optional):
- #address-cells: should be set to 1
- #size-cells: should be set to 1
Example for an AM33xx board:
gpmc: gpmc@50000000 {
compatible = "ti,am3352-gpmc";
ti,hwmods = "gpmc";
reg = <0x50000000 0x36c>;
interrupts = <100>;
gpmc,num-cs = <8>;
gpmc,num-waitpins = <2>;
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0x08000000 0x1000000>; /* CS0 space, 16MB */
elm_id = <&elm>;
interrupt-controller;
#interrupt-cells = <2>;
nand@0,0 {
compatible = "ti,omap2-nand";
reg = <0 0 4>; /* CS0, offset 0, NAND I/O window 4 */
interrupt-parent = <&gpmc>;
interrupts = <0 IRQ_TYPE_NONE>, <1 IRQ_TYPE NONE>;
nand-bus-width = <16>;
ti,nand-ecc-opt = "bch8";
ti,nand-xfer-type = "polled";
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
gpmc,sync-clk-ps = <0>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <44>;
gpmc,cs-wr-off-ns = <44>;
gpmc,adv-on-ns = <6>;
gpmc,adv-rd-off-ns = <34>;
gpmc,adv-wr-off-ns = <44>;
gpmc,we-off-ns = <40>;
gpmc,oe-off-ns = <54>;
gpmc,access-ns = <64>;
gpmc,rd-cycle-ns = <82>;
gpmc,wr-cycle-ns = <82>;
gpmc,wr-access-ns = <40>;
gpmc,wr-data-mux-bus-ns = <0>;
#address-cells = <1>;
#size-cells = <1>;
/* partitions go here */
};
};
How to select correct ECC scheme for your device ?
--------------------------------------------------
Higher ECC scheme usually means better protection against bit-flips and
increased system lifetime. However, selection of ECC scheme is dependent
on various other factors also like;
(1) support of built in hardware engines.
Some legacy OMAP SoC do not have ELM harware engine, so those SoC cannot
support ecc-schemes with hardware error-correction (BCHx_HW). However
such SoC can use ecc-schemes with software library for error-correction
(BCHx_HW_DETECTION_SW). The error correction capability with software
library remains equivalent to their hardware counter-part, but there is
slight CPU penalty when too many bit-flips are detected during reads.
(2) Device parameters like OOBSIZE.
Other factor which governs the selection of ecc-scheme is oob-size.
Higher ECC schemes require more OOB/Spare area to store ECC syndrome,
so the device should have enough free bytes available its OOB/Spare
area to accommodate ECC for entire page. In general following expression
helps in determining if given device can accommodate ECC syndrome:
"2 + (PAGESIZE / 512) * ECC_BYTES" <= OOBSIZE"
where
OOBSIZE number of bytes in OOB/spare area
PAGESIZE number of bytes in main-area of device page
ECC_BYTES number of ECC bytes generated to protect
512 bytes of data, which is:
'3' for HAM1_xx ecc schemes
'7' for BCH4_xx ecc schemes
'14' for BCH8_xx ecc schemes
'26' for BCH16_xx ecc schemes
Example(a): For a device with PAGESIZE = 2048 and OOBSIZE = 64 and
trying to use BCH16 (ECC_BYTES=26) ecc-scheme.
Number of ECC bytes per page = (2 + (2048 / 512) * 26) = 106 B
which is greater than capacity of NAND device (OOBSIZE=64)
Hence, BCH16 cannot be supported on given device. But it can
probably use lower ecc-schemes like BCH8.
Example(b): For a device with PAGESIZE = 2048 and OOBSIZE = 128 and
trying to use BCH16 (ECC_BYTES=26) ecc-scheme.
Number of ECC bytes per page = (2 + (2048 / 512) * 26) = 106 B
which can be accommodated in the OOB/Spare area of this device
(OOBSIZE=128). So this device can use BCH16 ecc-scheme.

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Documentation/devicetree/bindings/mtd/gpmc-nor.txt
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@@ -1,98 +0,0 @@
Device tree bindings for NOR flash connect to TI GPMC
NOR flash connected to the TI GPMC (found on OMAP boards) are represented as
child nodes of the GPMC controller with a name of "nor".
All timing relevant properties as well as generic GPMC child properties are
explained in a separate documents. Please refer to
Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
Required properties:
- bank-width: Width of NOR flash in bytes. GPMC supports 8-bit and
16-bit devices and so must be either 1 or 2 bytes.
- compatible: Documentation/devicetree/bindings/mtd/mtd-physmap.yaml
- gpmc,cs-on-ns: Chip-select assertion time
- gpmc,cs-rd-off-ns: Chip-select de-assertion time for reads
- gpmc,cs-wr-off-ns: Chip-select de-assertion time for writes
- gpmc,oe-on-ns: Output-enable assertion time
- gpmc,oe-off-ns: Output-enable de-assertion time
- gpmc,we-on-ns Write-enable assertion time
- gpmc,we-off-ns: Write-enable de-assertion time
- gpmc,access-ns: Start cycle to first data capture (read access)
- gpmc,rd-cycle-ns: Total read cycle time
- gpmc,wr-cycle-ns: Total write cycle time
- linux,mtd-name: Documentation/devicetree/bindings/mtd/mtd-physmap.yaml
- reg: Chip-select, base address (relative to chip-select)
and size of NOR flash. Note that base address will be
typically 0 as this is the start of the chip-select.
Optional properties:
- gpmc,XXX Additional GPMC timings and settings parameters. See
Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
Optional properties for partition table parsing:
- #address-cells: should be set to 1
- #size-cells: should be set to 1
Example:
gpmc: gpmc@6e000000 {
compatible = "ti,omap3430-gpmc", "simple-bus";
ti,hwmods = "gpmc";
reg = <0x6e000000 0x1000>;
interrupts = <20>;
gpmc,num-cs = <8>;
gpmc,num-waitpins = <4>;
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0x10000000 0x08000000>;
nor@0,0 {
compatible = "cfi-flash";
linux,mtd-name= "intel,pf48f6000m0y1be";
#address-cells = <1>;
#size-cells = <1>;
reg = <0 0 0x08000000>;
bank-width = <2>;
gpmc,mux-add-data;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <186>;
gpmc,cs-wr-off-ns = <186>;
gpmc,adv-on-ns = <12>;
gpmc,adv-rd-off-ns = <48>;
gpmc,adv-wr-off-ns = <48>;
gpmc,oe-on-ns = <54>;
gpmc,oe-off-ns = <168>;
gpmc,we-on-ns = <54>;
gpmc,we-off-ns = <168>;
gpmc,rd-cycle-ns = <186>;
gpmc,wr-cycle-ns = <186>;
gpmc,access-ns = <114>;
gpmc,page-burst-access-ns = <6>;
gpmc,bus-turnaround-ns = <12>;
gpmc,cycle2cycle-delay-ns = <18>;
gpmc,wr-data-mux-bus-ns = <90>;
gpmc,wr-access-ns = <186>;
gpmc,cycle2cycle-samecsen;
gpmc,cycle2cycle-diffcsen;
partition@0 {
label = "bootloader-nor";
reg = <0 0x40000>;
};
partition@40000 {
label = "params-nor";
reg = <0x40000 0x40000>;
};
partition@80000 {
label = "kernel-nor";
reg = <0x80000 0x200000>;
};
partition@280000 {
label = "filesystem-nor";
reg = <0x240000 0x7d80000>;
};
};
};

48
Documentation/devicetree/bindings/mtd/gpmc-onenand.txt
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@@ -1,48 +0,0 @@
Device tree bindings for GPMC connected OneNANDs
GPMC connected OneNAND (found on OMAP boards) are represented as child nodes of
the GPMC controller with a name of "onenand".
All timing relevant properties as well as generic gpmc child properties are
explained in a separate documents - please refer to
Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
Required properties:
- compatible: "ti,omap2-onenand"
- reg: The CS line the peripheral is connected to
- gpmc,device-width: Width of the ONENAND device connected to the GPMC
in bytes. Must be 1 or 2.
Optional properties:
- int-gpios: GPIO specifier for the INT pin.
For inline partition table parsing (optional):
- #address-cells: should be set to 1
- #size-cells: should be set to 1
Example for an OMAP3430 board:
gpmc: gpmc@6e000000 {
compatible = "ti,omap3430-gpmc";
ti,hwmods = "gpmc";
reg = <0x6e000000 0x1000000>;
interrupts = <20>;
gpmc,num-cs = <8>;
gpmc,num-waitpins = <4>;
#address-cells = <2>;
#size-cells = <1>;
onenand@0 {
compatible = "ti,omap2-onenand";
reg = <0 0 0>; /* CS0, offset 0 */
gpmc,device-width = <2>;
#address-cells = <1>;
#size-cells = <1>;
/* partitions go here */
};
};

121
Documentation/devicetree/bindings/mtd/ti,gpmc-nand.yaml Normal file
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@@ -0,0 +1,121 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/ti,gpmc-nand.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Texas Instruments GPMC NAND Flash controller.
maintainers:
- Tony Lindgren <tony@atomide.com>
- Roger Quadros <rogerq@kernel.org>
description:
GPMC NAND controller/Flash is represented as a child of the
GPMC controller node.
properties:
compatible:
const: ti,omap2-nand
reg:
maxItems: 1
interrupts:
items:
- description: Interrupt for fifoevent
- description: Interrupt for termcount
"#address-cells": true
"#size-cells": true
ti,nand-ecc-opt:
description: Desired ECC algorithm
$ref: /schemas/types.yaml#/definitions/string
enum: [sw, ham1, bch4, bch8, bch16]
ti,nand-xfer-type:
description: Data transfer method between controller and chip.
$ref: /schemas/types.yaml#/definitions/string
enum: [prefetch-polled, polled, prefetch-dma, prefetch-irq]
default: prefetch-polled
ti,elm-id:
description:
phandle to the ELM (Error Location Module).
$ref: /schemas/types.yaml#/definitions/phandle
nand-bus-width:
description:
Bus width to the NAND chip
$ref: /schemas/types.yaml#/definitions/uint32
enum: [8, 16]
default: 8
patternProperties:
"@[0-9a-f]+$":
$ref: "/schemas/mtd/partitions/partition.yaml"
allOf:
- $ref: "/schemas/memory-controllers/ti,gpmc-child.yaml"
required:
- compatible
- reg
- ti,nand-ecc-opt
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/gpio.h>
gpmc: memory-controller@50000000 {
compatible = "ti,am3352-gpmc";
dmas = <&edma 52 0>;
dma-names = "rxtx";
clocks = <&l3s_gclk>;
clock-names = "fck";
reg = <0x50000000 0x2000>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
gpmc,num-cs = <7>;
gpmc,num-waitpins = <2>;
#address-cells = <2>;
#size-cells = <1>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-controller;
#gpio-cells = <2>;
ranges = <0 0 0x08000000 0x01000000>; /* CS0 space. Min partition = 16MB */
nand@0,0 {
compatible = "ti,omap2-nand";
reg = <0 0 4>; /* device IO registers */
interrupt-parent = <&gpmc>;
interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
<1 IRQ_TYPE_NONE>; /* termcount */
ti,nand-xfer-type = "prefetch-dma";
ti,nand-ecc-opt = "bch16";
ti,elm-id = <&elm>;
#address-cells = <1>;
#size-cells = <1>;
/* NAND generic properties */
nand-bus-width = <8>;
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
/* GPMC properties*/
gpmc,device-width = <1>;
partition@0 {
label = "NAND.SPL";
reg = <0x00000000 0x00040000>;
};
partition@1 {
label = "NAND.SPL.backup1";
reg = <0x00040000 0x00040000>;
};
};
};

81
Documentation/devicetree/bindings/mtd/ti,gpmc-onenand.yaml Normal file
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@@ -0,0 +1,81 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/mtd/ti,gpmc-onenand.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: OneNAND over Texas Instruments GPMC bus.
maintainers:
- Tony Lindgren <tony@atomide.com>
- Roger Quadros <rogerq@kernel.org>
description:
GPMC connected OneNAND (found on OMAP boards) are represented
as child nodes of the GPMC controller.
properties:
compatible:
const: ti,omap2-onenand
reg:
items:
- description: |
Chip Select number, register offset and size of
OneNAND register window.
"#address-cells": true
"#size-cells": true
int-gpios:
description: GPIO specifier for the INT pin.
patternProperties:
"@[0-9a-f]+$":
$ref: "/schemas/mtd/partitions/partition.yaml"
allOf:
- $ref: "/schemas/memory-controllers/ti,gpmc-child.yaml"
required:
- compatible
- reg
- "#address-cells"
- "#size-cells"
unevaluatedProperties: false
examples:
- |
gpmc: memory-controller@6e000000 {
compatible = "ti,omap3430-gpmc";
reg = <0x6e000000 0x02d0>;
interrupts = <20>;
gpmc,num-cs = <8>;
gpmc,num-waitpins = <4>;
clocks = <&l3s_clkctrl>;
clock-names = "fck";
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0x01000000 0x01000000>, /* 16 MB for OneNAND */
<1 0 0x02000000 0x01000000>; /* 16 MB for smc91c96 */
onenand@0,0 {
compatible = "ti,omap2-onenand";
reg = <0 0 0x20000>; /* CS0, offset 0, IO size 128K */
#address-cells = <1>;
#size-cells = <1>;
partition@0 {
label = "bootloader";
reg = <0x00000000 0x00100000>;
};
partition@100000 {
label = "config";
reg = <0x00100000 0x002c0000>;
};
};
};

97
Documentation/devicetree/bindings/net/gpmc-eth.txt
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@@ -1,97 +0,0 @@
Device tree bindings for Ethernet chip connected to TI GPMC
Besides being used to interface with external memory devices, the
General-Purpose Memory Controller can be used to connect Pseudo-SRAM devices
such as ethernet controllers to processors using the TI GPMC as a data bus.
Ethernet controllers connected to TI GPMC are represented as child nodes of
the GPMC controller with an "ethernet" name.
All timing relevant properties as well as generic GPMC child properties are
explained in a separate documents. Please refer to
Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
For the properties relevant to the ethernet controller connected to the GPMC
refer to the binding documentation of the device. For example, the documentation
for the SMSC 911x is Documentation/devicetree/bindings/net/smsc,lan9115.yaml
Child nodes need to specify the GPMC bus address width using the "bank-width"
property but is possible that an ethernet controller also has a property to
specify the I/O registers address width. Even when the GPMC has a maximum 16-bit
address width, it supports devices with 32-bit word registers.
For example with an SMSC LAN911x/912x controller connected to the TI GPMC on an
OMAP2+ board, "bank-width = <2>;" and "reg-io-width = <4>;".
Required properties:
- bank-width: Address width of the device in bytes. GPMC supports 8-bit
and 16-bit devices and so must be either 1 or 2 bytes.
- compatible: Compatible string property for the ethernet child device.
- gpmc,cs-on-ns: Chip-select assertion time
- gpmc,cs-rd-off-ns: Chip-select de-assertion time for reads
- gpmc,cs-wr-off-ns: Chip-select de-assertion time for writes
- gpmc,oe-on-ns: Output-enable assertion time
- gpmc,oe-off-ns: Output-enable de-assertion time
- gpmc,we-on-ns: Write-enable assertion time
- gpmc,we-off-ns: Write-enable de-assertion time
- gpmc,access-ns: Start cycle to first data capture (read access)
- gpmc,rd-cycle-ns: Total read cycle time
- gpmc,wr-cycle-ns: Total write cycle time
- reg: Chip-select, base address (relative to chip-select)
and size of the memory mapped for the device.
Note that base address will be typically 0 as this
is the start of the chip-select.
Optional properties:
- gpmc,XXX Additional GPMC timings and settings parameters. See
Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
Example:
gpmc: gpmc@6e000000 {
compatible = "ti,omap3430-gpmc";
ti,hwmods = "gpmc";
reg = <0x6e000000 0x1000>;
interrupts = <20>;
gpmc,num-cs = <8>;
gpmc,num-waitpins = <4>;
#address-cells = <2>;
#size-cells = <1>;
ranges = <5 0 0x2c000000 0x1000000>;
ethernet@5,0 {
compatible = "smsc,lan9221", "smsc,lan9115";
reg = <5 0 0xff>;
bank-width = <2>;
gpmc,mux-add-data;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <186>;
gpmc,cs-wr-off-ns = <186>;
gpmc,adv-on-ns = <12>;
gpmc,adv-rd-off-ns = <48>;
gpmc,adv-wr-off-ns = <48>;
gpmc,oe-on-ns = <54>;
gpmc,oe-off-ns = <168>;
gpmc,we-on-ns = <54>;
gpmc,we-off-ns = <168>;
gpmc,rd-cycle-ns = <186>;
gpmc,wr-cycle-ns = <186>;
gpmc,access-ns = <114>;
gpmc,page-burst-access-ns = <6>;
gpmc,bus-turnaround-ns = <12>;
gpmc,cycle2cycle-delay-ns = <18>;
gpmc,wr-data-mux-bus-ns = <90>;
gpmc,wr-access-ns = <186>;
gpmc,cycle2cycle-samecsen;
gpmc,cycle2cycle-diffcsen;
interrupt-parent = <&gpio6>;
interrupts = <16>;
vmmc-supply = <&vddvario>;
vmmc_aux-supply = <&vdd33a>;
reg-io-width = <4>;
smsc,save-mac-address;
};
};

4
arch/arm/boot/dts/omap-gpmc-smsc911x.dtsi
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@@ -25,8 +25,8 @@ ethernet@gpmc {
compatible = "smsc,lan9221", "smsc,lan9115";
bank-width = <2>;
gpmc,device-width = <1>;
gpmc,cycle2cycle-samecsen = <1>;
gpmc,cycle2cycle-diffcsen = <1>;
gpmc,cycle2cycle-samecsen;
gpmc,cycle2cycle-diffcsen;
gpmc,cs-on-ns = <5>;
gpmc,cs-rd-off-ns = <150>;
gpmc,cs-wr-off-ns = <150>;

2
arch/arm/boot/dts/omap-gpmc-smsc9221.dtsi
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@@ -29,7 +29,7 @@ ethernet@gpmc {
compatible = "smsc,lan9221","smsc,lan9115";
bank-width = <2>;
gpmc,mux-add-data;
gpmc,mux-add-data = <0>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <42>;
gpmc,cs-wr-off-ns = <36>;

4
arch/arm/boot/dts/omap-zoom-common.dtsi
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@@ -27,8 +27,8 @@ uart@3,0 {
gpmc,mux-add-data = <0>;
gpmc,device-width = <1>;
gpmc,wait-pin = <1>;
gpmc,cycle2cycle-samecsen = <1>;
gpmc,cycle2cycle-diffcsen = <1>;
gpmc,cycle2cycle-samecsen;
gpmc,cycle2cycle-diffcsen;
gpmc,cs-on-ns = <5>;
gpmc,cs-rd-off-ns = <155>;
gpmc,cs-wr-off-ns = <155>;

4
arch/arm/boot/dts/omap2430-sdp.dts
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@@ -43,8 +43,8 @@ ethernet@gpmc {
gpmc,sync-clk-ps = <0>;
gpmc,mux-add-data = <2>;
gpmc,device-width = <1>;
gpmc,cycle2cycle-samecsen = <1>;
gpmc,cycle2cycle-diffcsen = <1>;
gpmc,cycle2cycle-samecsen;
gpmc,cycle2cycle-diffcsen;
gpmc,cs-on-ns = <6>;
gpmc,cs-rd-off-ns = <187>;
gpmc,cs-wr-off-ns = <187>;

4
arch/arm/boot/dts/omap3-devkit8000-common.dtsi
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@@ -267,8 +267,8 @@ ethernet@6,0 {
gpmc,mux-add-data = <0>;
gpmc,device-width = <1>;
gpmc,wait-pin = <0>;
gpmc,cycle2cycle-samecsen = <1>;
gpmc,cycle2cycle-diffcsen = <1>;
gpmc,cycle2cycle-samecsen;
gpmc,cycle2cycle-diffcsen;
gpmc,cs-on-ns = <6>;
gpmc,cs-rd-off-ns = <180>;

2
arch/arm/boot/dts/omap3-overo-tobiduo-common.dtsi
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@@ -22,7 +22,7 @@ smsc2: ethernet@4,0 {
compatible = "smsc,lan9221","smsc,lan9115";
bank-width = <2>;
gpmc,mux-add-data;
gpmc,mux-add-data = <0>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <42>;
gpmc,cs-wr-off-ns = <36>;

4
arch/arm/boot/dts/omap3-sb-t35.dtsi
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@@ -108,8 +108,8 @@ smsc2: ethernet@4,0 {
reg = <4 0 0xff>;
bank-width = <2>;
gpmc,device-width = <1>;
gpmc,cycle2cycle-samecsen = <1>;
gpmc,cycle2cycle-diffcsen = <1>;
gpmc,cycle2cycle-samecsen;
gpmc,cycle2cycle-diffcsen;
gpmc,cs-on-ns = <5>;
gpmc,cs-rd-off-ns = <150>;
gpmc,cs-wr-off-ns = <150>;