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drm/i915/lnl: Add gmbus/ddc support
LNL's south display uses the same table as MTP. Check for LNL's fake PCH to make it consistent with the other checks. The VBT table doesn't contain the VBT -> spec mapping for LNL. Like in other cases, uses the same as the previous platform. Bspec: 68971, 20124 Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20230919192128.2045154-18-lucas.demarchi@intel.com
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@@ -2194,7 +2194,8 @@ static u8 map_ddc_pin(struct drm_i915_private *i915, u8 vbt_pin)
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const u8 *ddc_pin_map;
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int i, n_entries;
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if (HAS_PCH_MTP(i915) || IS_ALDERLAKE_P(i915)) {
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if (INTEL_PCH_TYPE(i915) >= PCH_LNL || HAS_PCH_MTP(i915) ||
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IS_ALDERLAKE_P(i915)) {
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ddc_pin_map = adlp_ddc_pin_map;
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n_entries = ARRAY_SIZE(adlp_ddc_pin_map);
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} else if (IS_ALDERLAKE_S(i915)) {
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@@ -155,7 +155,10 @@ static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *i915,
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const struct gmbus_pin *pins;
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size_t size;
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if (INTEL_PCH_TYPE(i915) >= PCH_DG2) {
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if (INTEL_PCH_TYPE(i915) >= PCH_LNL) {
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pins = gmbus_pins_mtp;
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size = ARRAY_SIZE(gmbus_pins_mtp);
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} else if (INTEL_PCH_TYPE(i915) >= PCH_DG2) {
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pins = gmbus_pins_dg2;
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size = ARRAY_SIZE(gmbus_pins_dg2);
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} else if (INTEL_PCH_TYPE(i915) >= PCH_DG1) {
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