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staging: rtl8188eu: remove unused power flows and transitions
The driver defines a couple of "flows" to move the chip into a certain power state. Each flow is a sequence of "transitions". This patch removes flows and transitions which are not used. Signed-off-by: Martin Kaiser <martin@kaiser.cx> Link: https://lore.kernel.org/r/20210718173610.894-7-martin@kaiser.cx Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Martin Kaiser
committed by
Greg Kroah-Hartman
Greg Kroah-Hartman
parent
dff70f7fbe
commit
9d326c02ef
@@ -17,13 +17,6 @@ struct wl_pwr_cfg rtl8188E_power_on_flow[RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS +
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RTL8188E_TRANS_END
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};
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/* 3Radio off Array */
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struct wl_pwr_cfg rtl8188E_radio_off_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
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RTL8188E_TRANS_END_STEPS] = {
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RTL8188E_TRANS_ACT_TO_CARDEMU
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RTL8188E_TRANS_END
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};
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/* 3Card Disable Array */
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struct wl_pwr_cfg rtl8188E_card_disable_flow
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[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
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@@ -34,43 +27,6 @@ struct wl_pwr_cfg rtl8188E_card_disable_flow
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RTL8188E_TRANS_END
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};
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/* 3 Card Enable Array */
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struct wl_pwr_cfg rtl8188E_card_enable_flow
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[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
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RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS +
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RTL8188E_TRANS_END_STEPS] = {
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RTL8188E_TRANS_CARDDIS_TO_CARDEMU
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RTL8188E_TRANS_CARDEMU_TO_ACT
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RTL8188E_TRANS_END
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};
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/* 3Suspend Array */
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struct wl_pwr_cfg rtl8188E_suspend_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
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RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS +
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RTL8188E_TRANS_END_STEPS] = {
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RTL8188E_TRANS_ACT_TO_CARDEMU
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RTL8188E_TRANS_CARDEMU_TO_SUS
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RTL8188E_TRANS_END
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};
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/* 3 Resume Array */
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struct wl_pwr_cfg rtl8188E_resume_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
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RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS +
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RTL8188E_TRANS_END_STEPS] = {
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RTL8188E_TRANS_SUS_TO_CARDEMU
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RTL8188E_TRANS_CARDEMU_TO_ACT
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RTL8188E_TRANS_END
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};
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/* 3HWPDN Array */
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struct wl_pwr_cfg rtl8188E_hwpdn_flow[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
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RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS +
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RTL8188E_TRANS_END_STEPS] = {
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RTL8188E_TRANS_ACT_TO_CARDEMU
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RTL8188E_TRANS_CARDEMU_TO_PDN
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RTL8188E_TRANS_END
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};
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/* 3 Enter LPS */
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struct wl_pwr_cfg rtl8188E_enter_lps_flow[RTL8188E_TRANS_ACT_TO_LPS_STEPS +
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RTL8188E_TRANS_END_STEPS] = {
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@@ -78,11 +34,3 @@ struct wl_pwr_cfg rtl8188E_enter_lps_flow[RTL8188E_TRANS_ACT_TO_LPS_STEPS +
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RTL8188E_TRANS_ACT_TO_LPS
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RTL8188E_TRANS_END
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};
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/* 3 Leave LPS */
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struct wl_pwr_cfg rtl8188E_leave_lps_flow[RTL8188E_TRANS_LPS_TO_ACT_STEPS +
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RTL8188E_TRANS_END_STEPS] = {
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/* FW behavior */
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RTL8188E_TRANS_LPS_TO_ACT
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RTL8188E_TRANS_END
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};
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@@ -20,27 +20,12 @@
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* 4: LPS--Low Power State
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* 5: SUS--Suspend
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*
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* The transition from different states are defined below
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* TRANS_CARDEMU_TO_ACT
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* TRANS_ACT_TO_CARDEMU
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* TRANS_CARDEMU_TO_SUS
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* TRANS_SUS_TO_CARDEMU
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* TRANS_CARDEMU_TO_PDN
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* TRANS_ACT_TO_LPS
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* TRANS_LPS_TO_ACT
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*
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* TRANS_END
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*
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* PWR SEQ Version: rtl8188E_PwrSeq_V09.h
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*/
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#define RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS 10
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#define RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS 10
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#define RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS 10
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#define RTL8188E_TRANS_SUS_TO_CARDEMU_STEPS 10
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#define RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS 10
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#define RTL8188E_TRANS_PDN_TO_CARDEMU_STEPS 10
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#define RTL8188E_TRANS_ACT_TO_LPS_STEPS 15
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#define RTL8188E_TRANS_LPS_TO_ACT_STEPS 15
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#define RTL8188E_TRANS_END_STEPS 1
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#define RTL8188E_TRANS_CARDEMU_TO_ACT \
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@@ -81,30 +66,6 @@
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{0x0005, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, BIT(1), 0}, \
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/*wait till 0x04[9] = 0 polling until return 0 to disable*/
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#define RTL8188E_TRANS_CARDEMU_TO_SUS \
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/* format
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* { offset, cut_msk, cmd, msk,
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* value },
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* comments here
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*/ \
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{0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(3) | BIT(4), BIT(3)}, \
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/* 0x04[12:11] = 2b'01enable WL suspend */ \
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{0x0007, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, 0xFF, BIT(7)}, \
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/* 0x04[31:30] = 2b'10 enable enable bandgap mbias in suspend */\
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{0x0041, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4), 0}, \
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/*Clear SIC_EN register 0x40[12] = 1'b0 */ \
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{0xfe10, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4), BIT(4)}, \
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/*Set USB suspend enable local register 0xfe10[4]=1 */
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#define RTL8188E_TRANS_SUS_TO_CARDEMU \
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/* format
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* { offset, cut_msk, cmd, msk,
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* value },
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* comments here
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*/ \
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{0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(3) | BIT(4), 0}, \
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/*0x04[12:11] = 2b'01enable WL suspend*/
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#define RTL8188E_TRANS_CARDEMU_TO_CARDDIS \
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/* format
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* { offset, cut_msk, cmd, msk,
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@@ -122,35 +83,6 @@
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{0xfe10, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4), BIT(4)}, \
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/*Set USB suspend enable local register 0xfe10[4]=1 */
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#define RTL8188E_TRANS_CARDDIS_TO_CARDEMU \
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/* format
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* { offset, cut_msk, cmd, msk,
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* value },
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* comments here
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*/ \
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{0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(3) | BIT(4), 0}, \
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/*0x04[12:11] = 2b'01enable WL suspend*/
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#define RTL8188E_TRANS_CARDEMU_TO_PDN \
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/* format
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* { offset, cut_msk, cmd, msk,
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* value },
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* comments here
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*/ \
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{0x0006, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(0), 0}, \
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/* 0x04[16] = 0*/ \
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{0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(7), BIT(7)}, \
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/* 0x04[15] = 1*/
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#define RTL8188E_TRANS_PDN_TO_CARDEMU \
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/* format
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* { offset, cut_msk, cmd, msk,
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* value },
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* comments here
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*/ \
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{0x0005, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(7), 0}, \
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/* 0x04[15] = 0*/
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/* This is used by driver for LPSRadioOff Procedure, not for FW LPS Step */
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#define RTL8188E_TRANS_ACT_TO_LPS \
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/* format
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@@ -178,31 +110,6 @@
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{0x0553, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(5), BIT(5)}, \
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/*Respond TxOK to scheduler*/
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#define RTL8188E_TRANS_LPS_TO_ACT \
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/* format
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* { offset, cut_msk, cmd, msk,
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* value },
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* comments here
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*/ \
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{0xFE58, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, 0xFF, 0x84}, \
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/*USB RPWM*/ \
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{0x0002, PWR_CUT_ALL_MSK, PWR_CMD_DELAY, 0, PWRSEQ_DELAY_MS}, \
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/*Delay*/ \
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{0x0008, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(4), 0}, \
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/* 0x08[4] = 0 switch TSF to 40M */ \
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{0x0109, PWR_CUT_ALL_MSK, PWR_CMD_POLLING, BIT(7), 0}, \
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/* Polling 0x109[7]=0 TSF in 40M */ \
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{0x0029, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(6) | BIT(7), 0}, \
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/* 0x29[7:6] = 2b'00 enable BB clock */ \
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{0x0101, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, BIT(1), BIT(1)}, \
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/* 0x101[1] = 1 */ \
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{0x0100, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, 0xFF, 0xFF}, \
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/* 0x100[7:0] = 0xFF enable WMAC TRX */ \
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{0x0002, PWR_CUT_ALL_MSK, \
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PWR_CMD_WRITE, BIT(1) | BIT(0), BIT(1) | BIT(0)}, \
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/* 0x02[1:0] = 2b'11 enable BB macro */ \
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{0x0522, PWR_CUT_ALL_MSK, PWR_CMD_WRITE, 0xFF, 0}, /*. 0x522 = 0*/
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#define RTL8188E_TRANS_END \
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/* format
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* { offset, cut_msk, cmd, msk,
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@@ -213,30 +120,11 @@
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extern struct wl_pwr_cfg rtl8188E_power_on_flow
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[RTL8188E_TRANS_CARDEMU_TO_ACT_STEPS + RTL8188E_TRANS_END_STEPS];
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extern struct wl_pwr_cfg rtl8188E_radio_off_flow
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[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS + RTL8188E_TRANS_END_STEPS];
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extern struct wl_pwr_cfg rtl8188E_card_disable_flow
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[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
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RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS +
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RTL8188E_TRANS_END_STEPS];
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extern struct wl_pwr_cfg rtl8188E_card_enable_flow
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[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
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RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS +
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RTL8188E_TRANS_END_STEPS];
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extern struct wl_pwr_cfg rtl8188E_suspend_flow[
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RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
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RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS +
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RTL8188E_TRANS_END_STEPS];
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extern struct wl_pwr_cfg rtl8188E_resume_flow
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[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
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RTL8188E_TRANS_CARDEMU_TO_SUS_STEPS +
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RTL8188E_TRANS_END_STEPS];
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extern struct wl_pwr_cfg rtl8188E_hwpdn_flow
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[RTL8188E_TRANS_ACT_TO_CARDEMU_STEPS +
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RTL8188E_TRANS_CARDEMU_TO_PDN_STEPS + RTL8188E_TRANS_END_STEPS];
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extern struct wl_pwr_cfg rtl8188E_enter_lps_flow
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[RTL8188E_TRANS_ACT_TO_LPS_STEPS + RTL8188E_TRANS_END_STEPS];
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extern struct wl_pwr_cfg rtl8188E_leave_lps_flow
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[RTL8188E_TRANS_LPS_TO_ACT_STEPS + RTL8188E_TRANS_END_STEPS];
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#endif /* __HAL8188EPWRSEQ_H__ */
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@@ -22,14 +22,8 @@
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/* RTL8188E Power Configuration CMDs for USB/SDIO interfaces */
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#define Rtl8188E_NIC_PWR_ON_FLOW rtl8188E_power_on_flow
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#define Rtl8188E_NIC_RF_OFF_FLOW rtl8188E_radio_off_flow
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#define Rtl8188E_NIC_DISABLE_FLOW rtl8188E_card_disable_flow
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#define Rtl8188E_NIC_ENABLE_FLOW rtl8188E_card_enable_flow
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#define Rtl8188E_NIC_SUSPEND_FLOW rtl8188E_suspend_flow
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#define Rtl8188E_NIC_RESUME_FLOW rtl8188E_resume_flow
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#define Rtl8188E_NIC_PDN_FLOW rtl8188E_hwpdn_flow
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#define Rtl8188E_NIC_LPS_ENTER_FLOW rtl8188E_enter_lps_flow
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#define Rtl8188E_NIC_LPS_LEAVE_FLOW rtl8188E_leave_lps_flow
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#define DRVINFO_SZ 4 /* unit is 8bytes */
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#define PageNum_128(_Len) (u32)(((_Len) >> 7) + ((_Len) & 0x7F ? 1 : 0))
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