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drm/amdgpu/gfx: assign the actual me0 queues per pipe
Set the actual number of queues per pipe for ME0 (gfx). This way we will dump all of the queues properly in dev core dumps. Reviewed-by: Sunil Khatri <sunil.khatri@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@@ -4764,7 +4764,7 @@ static int gfx_v10_0_sw_init(struct amdgpu_ip_block *ip_block)
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case IP_VERSION(10, 1, 4):
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adev->gfx.me.num_me = 1;
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adev->gfx.me.num_pipe_per_me = 1;
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adev->gfx.me.num_queue_per_pipe = 1;
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adev->gfx.me.num_queue_per_pipe = 8;
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adev->gfx.mec.num_mec = 2;
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adev->gfx.mec.num_pipe_per_mec = 4;
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adev->gfx.mec.num_queue_per_pipe = 8;
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@@ -4779,7 +4779,7 @@ static int gfx_v10_0_sw_init(struct amdgpu_ip_block *ip_block)
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case IP_VERSION(10, 3, 7):
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adev->gfx.me.num_me = 1;
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adev->gfx.me.num_pipe_per_me = 2;
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adev->gfx.me.num_queue_per_pipe = 1;
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adev->gfx.me.num_queue_per_pipe = 2;
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adev->gfx.mec.num_mec = 2;
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adev->gfx.mec.num_pipe_per_mec = 4;
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adev->gfx.mec.num_queue_per_pipe = 4;
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@@ -1581,7 +1581,7 @@ static int gfx_v11_0_sw_init(struct amdgpu_ip_block *ip_block)
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case IP_VERSION(11, 0, 3):
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adev->gfx.me.num_me = 1;
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adev->gfx.me.num_pipe_per_me = 1;
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adev->gfx.me.num_queue_per_pipe = 1;
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adev->gfx.me.num_queue_per_pipe = 2;
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adev->gfx.mec.num_mec = 1;
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adev->gfx.mec.num_pipe_per_mec = 4;
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adev->gfx.mec.num_queue_per_pipe = 4;
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@@ -1594,7 +1594,7 @@ static int gfx_v11_0_sw_init(struct amdgpu_ip_block *ip_block)
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case IP_VERSION(11, 5, 3):
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adev->gfx.me.num_me = 1;
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adev->gfx.me.num_pipe_per_me = 1;
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adev->gfx.me.num_queue_per_pipe = 1;
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adev->gfx.me.num_queue_per_pipe = 2;
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adev->gfx.mec.num_mec = 1;
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adev->gfx.mec.num_pipe_per_mec = 4;
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adev->gfx.mec.num_queue_per_pipe = 4;
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@@ -1355,7 +1355,7 @@ static int gfx_v12_0_sw_init(struct amdgpu_ip_block *ip_block)
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case IP_VERSION(12, 0, 1):
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adev->gfx.me.num_me = 1;
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adev->gfx.me.num_pipe_per_me = 1;
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adev->gfx.me.num_queue_per_pipe = 1;
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adev->gfx.me.num_queue_per_pipe = 8;
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adev->gfx.mec.num_mec = 1;
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adev->gfx.mec.num_pipe_per_mec = 2;
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adev->gfx.mec.num_queue_per_pipe = 4;
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