Merge tag 'spi-fix-v7.2-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi

Pull spi fixes from Mark Brown:
 "A small set of fixes that came in since -rc1, we have one core fix for
  shutting down target mode properly if the system suspends while it's
  running plus a small set of fairly unremarkable device specific fixes.
  There's also a couple of pure DT binding changes for Renesas SoCs, the
  power domains one allows some SoCs to be correctly described with
  existing code"

* tag 'spi-fix-v7.2-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi:
  spi: rzv2h-rspi: Fix DMA transfer error handling for signal interruption
  spi: dt-bindings: snps,dw-apb-ssi: add 'power-domains' property
  spi: dt-bindings: snps,dw-apb-ssi: drop superfluous RZ/N1 entry
  spi: dw: use the correct error msg if request_irq() fails
  spi: dw: fix first spi transfer with dma always fallback to PIO
  spi: core: Abort active target transfer on controller suspend
  spi: sh-msiof: abort transfers when reset times out
This commit is contained in:
Linus Torvalds
2026-07-05 05:24:06 -10:00
6 changed files with 17 additions and 9 deletions

View File

@@ -50,7 +50,6 @@ properties:
- enum:
- mscc,ocelot-spi
- mscc,jaguar2-spi
- renesas,rzn1-spi
- sophgo,sg2042-spi
- thead,th1520-spi
- const: snps,dw-apb-ssi
@@ -94,6 +93,9 @@ properties:
- const: ssi_clk
- const: pclk
power-domains:
maxItems: 1
resets:
maxItems: 1

View File

@@ -949,7 +949,7 @@ int dw_spi_add_controller(struct device *dev, struct dw_spi *dws)
ret = request_irq(dws->irq, dw_spi_irq, IRQF_SHARED, dev_name(dev),
ctlr);
if (ret < 0 && ret != -ENOTCONN) {
dev_err(dev, "can not get IRQ\n");
dev_err(dev, "can not request IRQ\n");
goto err_free_ctlr;
}

View File

@@ -247,11 +247,12 @@ static bool dw_spi_can_dma(struct spi_controller *ctlr,
{
struct dw_spi *dws = spi_controller_get_devdata(ctlr);
enum dma_slave_buswidth dma_bus_width;
u8 n_bytes = roundup_pow_of_two(BITS_TO_BYTES(xfer->bits_per_word));
if (xfer->len <= dws->fifo_len)
return false;
dma_bus_width = dw_spi_dma_convert_width(dws->n_bytes);
dma_bus_width = dw_spi_dma_convert_width(n_bytes);
return dws->dma_addr_widths & BIT(dma_bus_width);
}

View File

@@ -366,14 +366,14 @@ static int rzv2h_rspi_transfer_dma(struct rzv2h_rspi_priv *rspi,
rzv2h_rspi_clear_all_irqs(rspi);
ret = wait_event_interruptible_timeout(rspi->wait, rspi->dma_callbacked, HZ);
if (ret) {
if (ret > 0) {
dmaengine_synchronize(rspi->controller->dma_tx);
dmaengine_synchronize(rspi->controller->dma_rx);
ret = 0;
} else {
dmaengine_terminate_sync(rspi->controller->dma_tx);
dmaengine_terminate_sync(rspi->controller->dma_rx);
ret = -ETIMEDOUT;
ret = ret ?: -ETIMEDOUT;
}
enable_irq(rspi->irq_rx);

View File

@@ -114,7 +114,7 @@ static irqreturn_t sh_msiof_spi_irq(int irq, void *data)
return IRQ_HANDLED;
}
static void sh_msiof_spi_reset_regs(struct sh_msiof_spi_priv *p)
static int sh_msiof_spi_reset_regs(struct sh_msiof_spi_priv *p)
{
u32 mask = SICTR_TXRST | SICTR_RXRST;
u32 data;
@@ -123,8 +123,8 @@ static void sh_msiof_spi_reset_regs(struct sh_msiof_spi_priv *p)
data |= mask;
sh_msiof_write(p, SICTR, data);
readl_poll_timeout_atomic(p->mapbase + SICTR, data, !(data & mask), 1,
100);
return readl_poll_timeout_atomic(p->mapbase + SICTR, data,
!(data & mask), 1, 100);
}
static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p,
@@ -834,7 +834,9 @@ static int sh_msiof_transfer_one(struct spi_controller *ctlr,
int ret;
/* reset registers */
sh_msiof_spi_reset_regs(p);
ret = sh_msiof_spi_reset_regs(p);
if (ret)
return ret;
/* setup clocks (clock already enabled in chipselect()) */
if (!spi_controller_is_target(p->ctlr))

View File

@@ -3670,6 +3670,9 @@ int spi_controller_suspend(struct spi_controller *ctlr)
{
int ret = 0;
if (ctlr->cur_msg && spi_controller_is_target(ctlr) && ctlr->target_abort)
ctlr->target_abort(ctlr);
/* Basically no-ops for non-queued controllers */
if (ctlr->queued) {
ret = spi_stop_queue(ctlr);