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https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2026-07-22 03:27:30 -04:00
Merge tag 'spi-fix-v7.2-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi
Pull spi fixes from Mark Brown: "A small set of fixes that came in since -rc1, we have one core fix for shutting down target mode properly if the system suspends while it's running plus a small set of fairly unremarkable device specific fixes. There's also a couple of pure DT binding changes for Renesas SoCs, the power domains one allows some SoCs to be correctly described with existing code" * tag 'spi-fix-v7.2-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi: spi: rzv2h-rspi: Fix DMA transfer error handling for signal interruption spi: dt-bindings: snps,dw-apb-ssi: add 'power-domains' property spi: dt-bindings: snps,dw-apb-ssi: drop superfluous RZ/N1 entry spi: dw: use the correct error msg if request_irq() fails spi: dw: fix first spi transfer with dma always fallback to PIO spi: core: Abort active target transfer on controller suspend spi: sh-msiof: abort transfers when reset times out
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@@ -50,7 +50,6 @@ properties:
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- enum:
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- mscc,ocelot-spi
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- mscc,jaguar2-spi
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- renesas,rzn1-spi
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- sophgo,sg2042-spi
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- thead,th1520-spi
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- const: snps,dw-apb-ssi
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@@ -94,6 +93,9 @@ properties:
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- const: ssi_clk
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- const: pclk
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power-domains:
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maxItems: 1
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resets:
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maxItems: 1
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@@ -949,7 +949,7 @@ int dw_spi_add_controller(struct device *dev, struct dw_spi *dws)
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ret = request_irq(dws->irq, dw_spi_irq, IRQF_SHARED, dev_name(dev),
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ctlr);
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if (ret < 0 && ret != -ENOTCONN) {
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dev_err(dev, "can not get IRQ\n");
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dev_err(dev, "can not request IRQ\n");
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goto err_free_ctlr;
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}
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@@ -247,11 +247,12 @@ static bool dw_spi_can_dma(struct spi_controller *ctlr,
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{
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struct dw_spi *dws = spi_controller_get_devdata(ctlr);
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enum dma_slave_buswidth dma_bus_width;
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u8 n_bytes = roundup_pow_of_two(BITS_TO_BYTES(xfer->bits_per_word));
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if (xfer->len <= dws->fifo_len)
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return false;
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dma_bus_width = dw_spi_dma_convert_width(dws->n_bytes);
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dma_bus_width = dw_spi_dma_convert_width(n_bytes);
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return dws->dma_addr_widths & BIT(dma_bus_width);
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}
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@@ -366,14 +366,14 @@ static int rzv2h_rspi_transfer_dma(struct rzv2h_rspi_priv *rspi,
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rzv2h_rspi_clear_all_irqs(rspi);
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ret = wait_event_interruptible_timeout(rspi->wait, rspi->dma_callbacked, HZ);
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if (ret) {
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if (ret > 0) {
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dmaengine_synchronize(rspi->controller->dma_tx);
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dmaengine_synchronize(rspi->controller->dma_rx);
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ret = 0;
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} else {
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dmaengine_terminate_sync(rspi->controller->dma_tx);
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dmaengine_terminate_sync(rspi->controller->dma_rx);
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ret = -ETIMEDOUT;
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ret = ret ?: -ETIMEDOUT;
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}
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enable_irq(rspi->irq_rx);
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@@ -114,7 +114,7 @@ static irqreturn_t sh_msiof_spi_irq(int irq, void *data)
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return IRQ_HANDLED;
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}
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static void sh_msiof_spi_reset_regs(struct sh_msiof_spi_priv *p)
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static int sh_msiof_spi_reset_regs(struct sh_msiof_spi_priv *p)
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{
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u32 mask = SICTR_TXRST | SICTR_RXRST;
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u32 data;
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@@ -123,8 +123,8 @@ static void sh_msiof_spi_reset_regs(struct sh_msiof_spi_priv *p)
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data |= mask;
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sh_msiof_write(p, SICTR, data);
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readl_poll_timeout_atomic(p->mapbase + SICTR, data, !(data & mask), 1,
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100);
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return readl_poll_timeout_atomic(p->mapbase + SICTR, data,
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!(data & mask), 1, 100);
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}
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static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p,
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@@ -834,7 +834,9 @@ static int sh_msiof_transfer_one(struct spi_controller *ctlr,
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int ret;
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/* reset registers */
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sh_msiof_spi_reset_regs(p);
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ret = sh_msiof_spi_reset_regs(p);
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if (ret)
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return ret;
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/* setup clocks (clock already enabled in chipselect()) */
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if (!spi_controller_is_target(p->ctlr))
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@@ -3670,6 +3670,9 @@ int spi_controller_suspend(struct spi_controller *ctlr)
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{
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int ret = 0;
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if (ctlr->cur_msg && spi_controller_is_target(ctlr) && ctlr->target_abort)
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ctlr->target_abort(ctlr);
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/* Basically no-ops for non-queued controllers */
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if (ctlr->queued) {
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ret = spi_stop_queue(ctlr);
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