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arm64: dts: qcom: x1e80100: enable GICv3 ITS for PCIe

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The DWC PCIe controller can be used with its internal MSI controller or
with an external one such as the GICv3 Interrupt Translation Service
(ITS).

Add the msi-map properties needed to use the GIC ITS. This will also
make Linux switch to the ITS implementation, which allows for assigning
affinity to individual MSIs. This specifically allows NVMe and Wi-Fi
interrupts to be processed on all cores (and not just on CPU0).

Note that using the GIC ITS on x1e80100 will cause Advanced Error
Reporting (AER) interrupts to be received on errors unlike when using
the internal MSI controller. Consequently, notifications about
(correctable) errors may now be logged for errors that previously went
unnoticed.

Also note that PCIe5 (and PCIe3) can currently only be used with the
internal MSI controller due to a platform (firmware) limitation.

Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20241009161715.14994-1-johan+linaro@kernel.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Johan Hovold
2024-10-09 18:17:15 +02:00
committed by Bjorn Andersson
parent 88e3d3266a
commit 9c4cd0aef2
1 changed files with 4 additions and 2 deletions
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6
arch/arm64/boot/dts/qcom/x1e80100.dtsi
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@@ -2934,6 +2934,8 @@ pcie6a: pci@1bf8000 {
linux,pci-domain = <6>;
num-lanes = <2>;
msi-map = <0x0 &gic_its 0xe0000 0x10000>;
interrupts = <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>,
@@ -3176,6 +3178,8 @@ pcie4: pci@1c08000 {
linux,pci-domain = <4>;
num-lanes = <2>;
msi-map = <0x0 &gic_its 0xc0000 0x10000>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
@@ -5766,8 +5770,6 @@ gic_its: msi-controller@17040000 {
msi-controller;
#msi-cells = <1>;
status = "disabled";
};
};