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Merge tag 'tegra-for-5.8-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/dt

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ARM: tegra: Device tree changes for v5.8-rc1

This contains a bit of cleanup and CPU frequency scaling support for the
Tegra30 Beaver board.

* tag 'tegra-for-5.8-arm-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  ARM: dts: tegra30: beaver: Add CPU Operating Performance Points
  ARM: dts: tegra30: beaver: Set up voltage regulators for DVFS
  ARM: tegra: Kill off "simple-panel" compatibles

Link: https://lore.kernel.org/r/20200515145311.1580134-11-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2020-05-21 22:34:59 +02:00
parent 22c328b1bc 94ea9681a9
commit 9c1acf5174
14 changed files with 50 additions and 17 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
arch/arm/boot/dts/tegra114-dalmore.dts
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@@ -46,8 +46,7 @@ dsi@54300000 {
avdd-dsi-csi-supply = <&avdd_1v2_reg>;
panel@0 {
compatible = "panasonic,vvx10f004b00",
"simple-panel";
compatible = "panasonic,vvx10f004b00";
reg = <0>;
power-supply = <&avdd_lcd_reg>;

2
arch/arm/boot/dts/tegra124-venice2.dts
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@@ -1087,7 +1087,7 @@ power {
};
panel: panel {
compatible = "lg,lp129qe", "simple-panel";
compatible = "lg,lp129qe";
backlight = <&backlight>;
ddc-i2c-bus = <&dpaux>;

2
arch/arm/boot/dts/tegra20-colibri-eval-v3.dts
View File

@@ -223,7 +223,7 @@ panel: panel {
* edt,et057090dhu: EDT 5.7" LCD TFT
* edt,et070080dh6: EDT 7.0" LCD TFT
*/
compatible = "edt,et057090dhu", "simple-panel";
compatible = "edt,et057090dhu";
backlight = <&backlight>;
power-supply = <&reg_3v3>;
};

2
arch/arm/boot/dts/tegra20-colibri-iris.dts
View File

@@ -205,7 +205,7 @@ panel: panel {
* edt,et057090dhu: EDT 5.7" LCD TFT
* edt,et070080dh6: EDT 7.0" LCD TFT
*/
compatible = "edt,et057090dhu", "simple-panel";
compatible = "edt,et057090dhu";
backlight = <&backlight>;
power-supply = <&reg_3v3>;
};

2
arch/arm/boot/dts/tegra20-harmony.dts
View File

@@ -665,7 +665,7 @@ power {
};
panel: panel {
compatible = "auo,b101aw03", "simple-panel";
compatible = "auo,b101aw03";
power-supply = <&vdd_pnl_reg>;
enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>;

2
arch/arm/boot/dts/tegra20-medcom-wide.dts
View File

@@ -57,7 +57,7 @@ backlight: backlight {
};
panel: panel {
compatible = "innolux,n156bge-l21", "simple-panel";
compatible = "innolux,n156bge-l21";
power-supply = <&vdd_1v8_reg>, <&vdd_3v3_reg>;
enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>;

2
arch/arm/boot/dts/tegra20-paz00.dts
View File

@@ -604,7 +604,7 @@ wifi {
};
panel: panel {
compatible = "samsung,ltn101nt05", "simple-panel";
compatible = "samsung,ltn101nt05";
ddc-i2c-bus = <&lvds_ddc>;
power-supply = <&vdd_pnl_reg>;

2
arch/arm/boot/dts/tegra20-seaboard.dts
View File

@@ -826,7 +826,7 @@ lid {
};
panel: panel {
compatible = "chunghwa,claa101wa01a", "simple-panel";
compatible = "chunghwa,claa101wa01a";
power-supply = <&vdd_pnl_reg>;
enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>;

2
arch/arm/boot/dts/tegra20-ventana.dts
View File

@@ -611,7 +611,7 @@ power {
};
panel: panel {
compatible = "chunghwa,claa101wa01a", "simple-panel";
compatible = "chunghwa,claa101wa01a";
power-supply = <&vdd_pnl_reg>;
enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>;

2
arch/arm/boot/dts/tegra30-apalis-eval.dts
View File

@@ -195,7 +195,7 @@ panel: panel {
* edt,et057090dhu: EDT 5.7" LCD TFT
* edt,et070080dh6: EDT 7.0" LCD TFT
*/
compatible = "edt,et057090dhu", "simple-panel";
compatible = "edt,et057090dhu";
backlight = <&backlight>;
power-supply = <&reg_3v3>;
};

2
arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts
View File

@@ -196,7 +196,7 @@ panel: panel {
* edt,et057090dhu: EDT 5.7" LCD TFT
* edt,et070080dh6: EDT 7.0" LCD TFT
*/
compatible = "edt,et057090dhu", "simple-panel";
compatible = "edt,et057090dhu";
backlight = <&backlight>;
power-supply = <&reg_3v3>;
};

40
arch/arm/boot/dts/tegra30-beaver.dts
View File

@@ -2,6 +2,8 @@
/dts-v1/;
#include "tegra30.dtsi"
#include "tegra30-cpu-opp.dtsi"
#include "tegra30-cpu-opp-microvolt.dtsi"
/ {
model = "NVIDIA Tegra30 Beaver evaluation board";
@@ -1806,9 +1808,14 @@ vdd2_reg: vdd2 {
vddctrl_reg: vddctrl {
regulator-name = "vdd_cpu,vdd_sys";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1000000>;
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1250000>;
regulator-coupled-with = <&core_vdd_reg>;
regulator-coupled-max-spread = <300000>;
regulator-max-step-microvolt = <100000>;
regulator-always-on;
nvidia,tegra-cpu-regulator;
};
vio_reg: vio {
@@ -1868,17 +1875,22 @@ ldo8_reg: ldo8 {
};
};
tps62361@60 {
core_vdd_reg: tps62361@60 {
compatible = "ti,tps62361";
reg = <0x60>;
regulator-name = "tps62361-vout";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1500000>;
regulator-coupled-with = <&vddctrl_reg>;
regulator-coupled-max-spread = <300000>;
regulator-max-step-microvolt = <100000>;
regulator-boot-on;
regulator-always-on;
ti,vsel0-state-high;
ti,vsel1-state-high;
nvidia,tegra-core-regulator;
};
};
@@ -2120,4 +2132,26 @@ sound {
assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
<&tegra_car TEGRA30_CLK_EXTERN1>;
};
cpus {
cpu0: cpu@0 {
cpu-supply = <&vddctrl_reg>;
operating-points-v2 = <&cpu0_opp_table>;
};
cpu@1 {
cpu-supply = <&vddctrl_reg>;
operating-points-v2 = <&cpu0_opp_table>;
};
cpu@2 {
cpu-supply = <&vddctrl_reg>;
operating-points-v2 = <&cpu0_opp_table>;
};
cpu@3 {
cpu-supply = <&vddctrl_reg>;
operating-points-v2 = <&cpu0_opp_table>;
};
};
};

2
arch/arm/boot/dts/tegra30-cardhu.dtsi
View File

@@ -432,7 +432,7 @@ clk32k_in: clock@0 {
};
panel: panel {
compatible = "chunghwa,claa101wb01", "simple-panel";
compatible = "chunghwa,claa101wb01";
ddc-i2c-bus = <&panelddc>;
power-supply = <&vdd_pnl1_reg>;

2
arch/arm/boot/dts/tegra30-colibri-eval-v3.dts
View File

@@ -159,7 +159,7 @@ panel: panel {
* edt,et057090dhu: EDT 5.7" LCD TFT
* edt,et070080dh6: EDT 7.0" LCD TFT
*/
compatible = "edt,et057090dhu", "simple-panel";
compatible = "edt,et057090dhu";
backlight = <&backlight>;
power-supply = <&reg_3v3>;
};