mirrors/linux
2
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git synced 2026-08-31 07:03:28 -04:00
Code Issues Packages Projects Releases Wiki Activity

perf cs-etm: Refactor instruction size handling

Browse Source 
This patch introduces a new function cs_etm__instr_size() to calculate
the instruction size based on ISA type and instruction address.

Given the trace data can be MB and most likely that will be A64/A32 on
a lot of platforms, cs_etm__instr_addr() keeps a single ISA type check
for A64/A32 and executes an optimized calculation (addr + offset * 4).

Signed-off-by: Leo Yan <leo.yan@linaro.org>
Reviewed-by: James Clark <james.clark@linaro.org>
Signed-off-by: Leo Yan <leo.yan@arm.com>
Signed-off-by: Namhyung Kim <namhyung@kernel.org>
This commit is contained in:
Leo Yan
2026-07-02 20:51:39 +01:00
committed by Namhyung Kim
parent 5cf3ea0f26
commit 9bb1423295
1 changed files with 22 additions and 21 deletions
Download Patch File Download Diff File Expand all files Collapse all files

43
tools/perf/util/cs-etm.c
View File

@@ -1389,6 +1389,18 @@ static inline int cs_etm__t32_instr_size(struct cs_etm_queue *etmq,
return ((instrBytes[1] & 0xF8) >= 0xE8) ? 4 : 2;
}
static inline int cs_etm__instr_size(struct cs_etm_queue *etmq,
struct cs_etm_traceid_queue *tidq,
struct cs_etm_packet *packet,
u64 addr)
{
if (packet->isa == CS_ETM_ISA_T32)
return cs_etm__t32_instr_size(etmq, tidq, packet, addr);
/* Otherwise, 4-byte instruction size for A32/A64 */
return 4;
}
static inline u64 cs_etm__first_executed_instr(struct cs_etm_packet *packet)
{
/*
@@ -1417,19 +1429,17 @@ static inline u64 cs_etm__instr_addr(struct cs_etm_queue *etmq,
struct cs_etm_packet *packet,
u64 offset)
{
if (packet->isa == CS_ETM_ISA_T32) {
u64 addr = packet->start_addr;
u64 addr = packet->start_addr;
while (offset) {
addr += cs_etm__t32_instr_size(etmq, tidq, packet,
addr);
offset--;
}
return addr;
/* 4-byte instruction size for A32/A64 */
if (packet->isa == CS_ETM_ISA_A64 || packet->isa == CS_ETM_ISA_A32)
return addr + offset * 4;
while (offset) {
addr += cs_etm__instr_size(etmq, tidq, packet, addr);
offset--;
}
/* Assume a 4 byte instruction size (A32/A64) */
return packet->start_addr + offset * 4;
return addr;
}
static void cs_etm__update_last_branch_rb(struct cs_etm_queue *etmq,
@@ -1599,16 +1609,7 @@ static void cs_etm__copy_insn(struct cs_etm_queue *etmq,
return;
}
/*
* T32 instruction size might be 32-bit or 16-bit, decide by calling
* cs_etm__t32_instr_size().
*/
if (packet->isa == CS_ETM_ISA_T32)
sample->insn_len = cs_etm__t32_instr_size(etmq, tidq, packet,
sample->ip);
/* Otherwise, A64 and A32 instruction size are always 32-bit. */
else
sample->insn_len = 4;
sample->insn_len = cs_etm__instr_size(etmq, tidq, packet, sample->ip);
cs_etm__frontend_mem_access(etmq, tidq, packet, sample->ip,
sample->insn_len, (void *)sample->insn);