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drm/i915/pvc: Adjust EU per SS according to HAS_ONE_EU_PER_FUSE_BIT()

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If we're treating each bit in the EU fuse register as a single EU
instead of a pair of EUs, then that also cuts the number of potential
EUs per subslice in half.

Fixes: 5ac342ef84 ("drm/i915/pvc: Add SSEU changes")
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220610230801.459577-1-matthew.d.roper@intel.com
This commit is contained in:
Matt Roper
2022-06-10 16:08:01 -07:00
parent e0d7371b46
commit 9affc1b87e
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/drm/i915/gt/intel_sseu.c
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@@ -229,7 +229,7 @@ static void xehp_sseu_info_init(struct intel_gt *gt)
*/
intel_sseu_set_info(sseu, 1,
32 * max(num_geometry_regs, num_compute_regs),
16);
HAS_ONE_EU_PER_FUSE_BIT(gt->i915) ? 8 : 16);
sseu->has_xehp_dss = 1;
xehp_load_dss_mask(uncore, &sseu->geometry_subslice_mask,