mirrors/linux
2
0
Fork 0
mirror of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git synced 2026-07-22 02:17:36 -04:00
Code Issues Packages Projects Releases Wiki Activity

dt-bindings: clock: qcom: Add X1P42100 video clock controller

Browse Source 
Add device tree bindings for the video clock controller on Qualcomm
X1P42100 (Purwa) SoC.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260507-purwa-videocc-camcc-v5-1-fc3af4130282@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Jagadeesh Kona
2026-05-07 11:08:26 +05:30
committed by Bjorn Andersson
parent 9bee0a0a33
commit 9ae38c6919
2 changed files with 51 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
View File

@@ -20,6 +20,7 @@ description: |
include/dt-bindings/clock/qcom,sm8450-videocc.h
include/dt-bindings/clock/qcom,sm8650-videocc.h
include/dt-bindings/clock/qcom,sm8750-videocc.h
include/dt-bindings/clock/qcom,x1p42100-videocc.h
properties:
compatible:
@@ -32,6 +33,7 @@ properties:
- qcom,sm8650-videocc
- qcom,sm8750-videocc
- qcom,x1e80100-videocc
- qcom,x1p42100-videocc
clocks:
items:
@@ -70,6 +72,7 @@ allOf:
- qcom,sm8450-videocc
- qcom,sm8550-videocc
- qcom,sm8750-videocc
- qcom,x1p42100-videocc
then:
required:
- required-opps

48
include/dt-bindings/clock/qcom,x1p42100-videocc.h Normal file
View File

@@ -0,0 +1,48 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_X1P42100_H
#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_X1P42100_H
/* VIDEO_CC clocks */
#define VIDEO_CC_MVS0_CLK 0
#define VIDEO_CC_MVS0_CLK_SRC 1
#define VIDEO_CC_MVS0_DIV_CLK_SRC 2
#define VIDEO_CC_MVS0C_CLK 3
#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC 4
#define VIDEO_CC_MVS1_CLK 5
#define VIDEO_CC_MVS1_CLK_SRC 6
#define VIDEO_CC_MVS1_DIV_CLK_SRC 7
#define VIDEO_CC_MVS1C_CLK 8
#define VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC 9
#define VIDEO_CC_PLL0 10
#define VIDEO_CC_PLL1 11
#define VIDEO_CC_MVS0_SHIFT_CLK 12
#define VIDEO_CC_MVS0C_SHIFT_CLK 13
#define VIDEO_CC_MVS1_SHIFT_CLK 14
#define VIDEO_CC_MVS1C_SHIFT_CLK 15
#define VIDEO_CC_XO_CLK_SRC 16
#define VIDEO_CC_MVS0_BSE_CLK 17
#define VIDEO_CC_MVS0_BSE_CLK_SRC 18
#define VIDEO_CC_MVS0_BSE_DIV4_DIV_CLK_SRC 19
/* VIDEO_CC power domains */
#define VIDEO_CC_MVS0C_GDSC 0
#define VIDEO_CC_MVS0_GDSC 1
#define VIDEO_CC_MVS1C_GDSC 2
#define VIDEO_CC_MVS1_GDSC 3
/* VIDEO_CC resets */
#define CVP_VIDEO_CC_INTERFACE_BCR 0
#define CVP_VIDEO_CC_MVS0_BCR 1
#define CVP_VIDEO_CC_MVS0C_BCR 2
#define CVP_VIDEO_CC_MVS1_BCR 3
#define CVP_VIDEO_CC_MVS1C_BCR 4
#define VIDEO_CC_MVS0C_CLK_ARES 5
#define VIDEO_CC_MVS1C_CLK_ARES 6
#define VIDEO_CC_XO_CLK_ARES 7
#define VIDEO_CC_MVS0_BSE_BCR 8
#endif