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Merge tag 'memory-controller-drv-renesas-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into soc/drivers

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Renesas memory controller drivers for v6.16

Improvements and new device support for the Renesas RPC IF memory
controller driver:
1. Minor cleanup and improvements.
2. Refactor the driver to accommodate for newly added Renesas RZ/G3E support:
   - Acquire two resets instead of only one,
   - Add RZ/G3E xSPI support with different register layout and its own,
     new interface for Renesas SPI.

* tag 'memory-controller-drv-renesas-6.16' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl:
  memory: renesas-rpc-if: Add missing static keyword
  memory: renesas-rpc-if: Add RZ/G3E xSPI support
  memory: renesas-rpc-if: Add wrapper functions
  memory: renesas-rpc-if: Add regmap to struct rpcif_info
  memory: renesas-rpc-if: Use devm_reset_control_array_get_exclusive()
  memory: renesas-rpc-if: Move rpc-if reg definitions
  dt-bindings: memory: Document RZ/G3E support
  memory: renesas-rpc-if: Move rpcif_info definitions near to the user
  memory: renesas-rpc-if: Fix RPCIF_DRENR_CDB macro error

Link: https://lore.kernel.org/r/20250508090749.51379-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2025-05-09 23:10:31 +02:00
parent 4e61c011b0 798dc3f19c
commit 9a977b01fb
5 changed files with 914 additions and 191 deletions
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135
Documentation/devicetree/bindings/memory-controllers/renesas,rzg3e-xspi.yaml Normal file
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@@ -0,0 +1,135 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/memory-controllers/renesas,rzg3e-xspi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas Expanded Serial Peripheral Interface (xSPI)
maintainers:
- Biju Das <biju.das.jz@bp.renesas.com>
description: |
Renesas xSPI allows a SPI flash connected to the SoC to be accessed via
the memory-mapping or the manual command mode.
The flash chip itself should be represented by a subnode of the XSPI node.
The flash interface is selected based on the "compatible" property of this
subnode:
- "jedec,spi-nor";
allOf:
- $ref: /schemas/spi/spi-controller.yaml#
properties:
compatible:
const: renesas,r9a09g047-xspi # RZ/G3E
reg:
items:
- description: xSPI registers
- description: direct mapping area
reg-names:
items:
- const: regs
- const: dirmap
interrupts:
items:
- description: Interrupt pulse signal by factors excluding errors
- description: Interrupt pulse signal by error factors
interrupt-names:
items:
- const: pulse
- const: err_pulse
clocks:
items:
- description: AHB clock
- description: AXI clock
- description: SPI clock
- description: Double speed SPI clock
clock-names:
items:
- const: ahb
- const: axi
- const: spi
- const: spix2
power-domains:
maxItems: 1
resets:
items:
- description: Hardware reset
- description: AXI reset
reset-names:
items:
- const: hresetn
- const: aresetn
renesas,xspi-cs-addr-sys:
$ref: /schemas/types.yaml#/definitions/phandle
description: |
Phandle to the system controller (sys) that allows to configure
xSPI CS0 and CS1 addresses.
patternProperties:
"flash@[0-9a-f]+$":
type: object
additionalProperties: true
properties:
compatible:
contains:
const: jedec,spi-nor
required:
- compatible
- reg
- reg-names
- interrupts
- interrupt-names
- clocks
- clock-names
- power-domains
- resets
- reset-names
- '#address-cells'
- '#size-cells'
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/renesas,r9a09g047-cpg.h>
spi@11030000 {
compatible = "renesas,r9a09g047-xspi";
reg = <0x11030000 0x10000>, <0x20000000 0x10000000>;
reg-names = "regs", "dirmap";
interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 229 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "pulse", "err_pulse";
clocks = <&cpg CPG_MOD 0x9f>, <&cpg CPG_MOD 0xa0>,
<&cpg CPG_CORE 9>, <&cpg CPG_MOD 0xa1>;
clock-names = "ahb", "axi", "spi", "spix2";
power-domains = <&cpg>;
resets = <&cpg 0xa3>, <&cpg 0xa4>;
reset-names = "hresetn", "aresetn";
#address-cells = <1>;
#size-cells = <0>;
flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <40000000>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
};
};

147
drivers/memory/renesas-rpc-if-regs.h Normal file
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@@ -0,0 +1,147 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* R-Car RPC Interface Registers Definitions
*
* Copyright (C) 2025 Renesas Electronics Corporation
*/
#ifndef __RENESAS_RPC_IF_REGS_H__
#define __RENESAS_RPC_IF_REGS_H__
#include <linux/bits.h>
#define RPCIF_CMNCR 0x0000 /* R/W */
#define RPCIF_CMNCR_MD BIT(31)
#define RPCIF_CMNCR_MOIIO3(val) (((val) & 0x3) << 22)
#define RPCIF_CMNCR_MOIIO2(val) (((val) & 0x3) << 20)
#define RPCIF_CMNCR_MOIIO1(val) (((val) & 0x3) << 18)
#define RPCIF_CMNCR_MOIIO0(val) (((val) & 0x3) << 16)
#define RPCIF_CMNCR_MOIIO(val) (RPCIF_CMNCR_MOIIO0(val) | RPCIF_CMNCR_MOIIO1(val) | \
RPCIF_CMNCR_MOIIO2(val) | RPCIF_CMNCR_MOIIO3(val))
#define RPCIF_CMNCR_IO3FV(val) (((val) & 0x3) << 14) /* documented for RZ/G2L */
#define RPCIF_CMNCR_IO2FV(val) (((val) & 0x3) << 12) /* documented for RZ/G2L */
#define RPCIF_CMNCR_IO0FV(val) (((val) & 0x3) << 8)
#define RPCIF_CMNCR_IOFV(val) (RPCIF_CMNCR_IO0FV(val) | RPCIF_CMNCR_IO2FV(val) | \
RPCIF_CMNCR_IO3FV(val))
#define RPCIF_CMNCR_BSZ(val) (((val) & 0x3) << 0)
#define RPCIF_SSLDR 0x0004 /* R/W */
#define RPCIF_SSLDR_SPNDL(d) (((d) & 0x7) << 16)
#define RPCIF_SSLDR_SLNDL(d) (((d) & 0x7) << 8)
#define RPCIF_SSLDR_SCKDL(d) (((d) & 0x7) << 0)
#define RPCIF_DRCR 0x000C /* R/W */
#define RPCIF_DRCR_SSLN BIT(24)
#define RPCIF_DRCR_RBURST(v) ((((v) - 1) & 0x1F) << 16)
#define RPCIF_DRCR_RCF BIT(9)
#define RPCIF_DRCR_RBE BIT(8)
#define RPCIF_DRCR_SSLE BIT(0)
#define RPCIF_DRCMR 0x0010 /* R/W */
#define RPCIF_DRCMR_CMD(c) (((c) & 0xFF) << 16)
#define RPCIF_DRCMR_OCMD(c) (((c) & 0xFF) << 0)
#define RPCIF_DREAR 0x0014 /* R/W */
#define RPCIF_DREAR_EAV(c) (((c) & 0xF) << 16)
#define RPCIF_DREAR_EAC(c) (((c) & 0x7) << 0)
#define RPCIF_DROPR 0x0018 /* R/W */
#define RPCIF_DRENR 0x001C /* R/W */
#define RPCIF_DRENR_CDB(o) (((u32)((o) & 0x3)) << 30)
#define RPCIF_DRENR_OCDB(o) (((o) & 0x3) << 28)
#define RPCIF_DRENR_ADB(o) (((o) & 0x3) << 24)
#define RPCIF_DRENR_OPDB(o) (((o) & 0x3) << 20)
#define RPCIF_DRENR_DRDB(o) (((o) & 0x3) << 16)
#define RPCIF_DRENR_DME BIT(15)
#define RPCIF_DRENR_CDE BIT(14)
#define RPCIF_DRENR_OCDE BIT(12)
#define RPCIF_DRENR_ADE(v) (((v) & 0xF) << 8)
#define RPCIF_DRENR_OPDE(v) (((v) & 0xF) << 4)
#define RPCIF_SMCR 0x0020 /* R/W */
#define RPCIF_SMCR_SSLKP BIT(8)
#define RPCIF_SMCR_SPIRE BIT(2)
#define RPCIF_SMCR_SPIWE BIT(1)
#define RPCIF_SMCR_SPIE BIT(0)
#define RPCIF_SMCMR 0x0024 /* R/W */
#define RPCIF_SMCMR_CMD(c) (((c) & 0xFF) << 16)
#define RPCIF_SMCMR_OCMD(c) (((c) & 0xFF) << 0)
#define RPCIF_SMADR 0x0028 /* R/W */
#define RPCIF_SMOPR 0x002C /* R/W */
#define RPCIF_SMOPR_OPD3(o) (((o) & 0xFF) << 24)
#define RPCIF_SMOPR_OPD2(o) (((o) & 0xFF) << 16)
#define RPCIF_SMOPR_OPD1(o) (((o) & 0xFF) << 8)
#define RPCIF_SMOPR_OPD0(o) (((o) & 0xFF) << 0)
#define RPCIF_SMENR 0x0030 /* R/W */
#define RPCIF_SMENR_CDB(o) (((o) & 0x3) << 30)
#define RPCIF_SMENR_OCDB(o) (((o) & 0x3) << 28)
#define RPCIF_SMENR_ADB(o) (((o) & 0x3) << 24)
#define RPCIF_SMENR_OPDB(o) (((o) & 0x3) << 20)
#define RPCIF_SMENR_SPIDB(o) (((o) & 0x3) << 16)
#define RPCIF_SMENR_DME BIT(15)
#define RPCIF_SMENR_CDE BIT(14)
#define RPCIF_SMENR_OCDE BIT(12)
#define RPCIF_SMENR_ADE(v) (((v) & 0xF) << 8)
#define RPCIF_SMENR_OPDE(v) (((v) & 0xF) << 4)
#define RPCIF_SMENR_SPIDE(v) (((v) & 0xF) << 0)
#define RPCIF_SMRDR0 0x0038 /* R */
#define RPCIF_SMRDR1 0x003C /* R */
#define RPCIF_SMWDR0 0x0040 /* W */
#define RPCIF_SMWDR1 0x0044 /* W */
#define RPCIF_CMNSR 0x0048 /* R */
#define RPCIF_CMNSR_SSLF BIT(1)
#define RPCIF_CMNSR_TEND BIT(0)
#define RPCIF_DRDMCR 0x0058 /* R/W */
#define RPCIF_DMDMCR_DMCYC(v) ((((v) - 1) & 0x1F) << 0)
#define RPCIF_DRDRENR 0x005C /* R/W */
#define RPCIF_DRDRENR_HYPE(v) (((v) & 0x7) << 12)
#define RPCIF_DRDRENR_ADDRE BIT(8)
#define RPCIF_DRDRENR_OPDRE BIT(4)
#define RPCIF_DRDRENR_DRDRE BIT(0)
#define RPCIF_SMDMCR 0x0060 /* R/W */
#define RPCIF_SMDMCR_DMCYC(v) ((((v) - 1) & 0x1F) << 0)
#define RPCIF_SMDRENR 0x0064 /* R/W */
#define RPCIF_SMDRENR_HYPE(v) (((v) & 0x7) << 12)
#define RPCIF_SMDRENR_ADDRE BIT(8)
#define RPCIF_SMDRENR_OPDRE BIT(4)
#define RPCIF_SMDRENR_SPIDRE BIT(0)
#define RPCIF_PHYADD 0x0070 /* R/W available on R-Car E3/D3/V3M and RZ/G2{E,L} */
#define RPCIF_PHYWR 0x0074 /* R/W available on R-Car E3/D3/V3M and RZ/G2{E,L} */
#define RPCIF_PHYCNT 0x007C /* R/W */
#define RPCIF_PHYCNT_CAL BIT(31)
#define RPCIF_PHYCNT_OCTA(v) (((v) & 0x3) << 22)
#define RPCIF_PHYCNT_EXDS BIT(21)
#define RPCIF_PHYCNT_OCT BIT(20)
#define RPCIF_PHYCNT_DDRCAL BIT(19)
#define RPCIF_PHYCNT_HS BIT(18)
#define RPCIF_PHYCNT_CKSEL(v) (((v) & 0x3) << 16) /* valid only for RZ/G2L */
#define RPCIF_PHYCNT_STRTIM(v) (((v) & 0x7) << 15 | ((v) & 0x8) << 24) /* valid for R-Car and RZ/G2{E,H,M,N} */
#define RPCIF_PHYCNT_WBUF2 BIT(4)
#define RPCIF_PHYCNT_WBUF BIT(2)
#define RPCIF_PHYCNT_PHYMEM(v) (((v) & 0x3) << 0)
#define RPCIF_PHYCNT_PHYMEM_MASK GENMASK(1, 0)
#define RPCIF_PHYOFFSET1 0x0080 /* R/W */
#define RPCIF_PHYOFFSET1_DDRTMG(v) (((v) & 0x3) << 28)
#define RPCIF_PHYOFFSET2 0x0084 /* R/W */
#define RPCIF_PHYOFFSET2_OCTTMG(v) (((v) & 0x7) << 8)
#define RPCIF_PHYINT 0x0088 /* R/W */
#define RPCIF_PHYINT_WPVAL BIT(1)
#endif /* __RENESAS_RPC_IF_REGS_H__ */

714
drivers/memory/renesas-rpc-if.c
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@@ -18,139 +18,8 @@
#include <memory/renesas-rpc-if.h>
#define RPCIF_CMNCR 0x0000 /* R/W */
#define RPCIF_CMNCR_MD BIT(31)
#define RPCIF_CMNCR_MOIIO3(val) (((val) & 0x3) << 22)
#define RPCIF_CMNCR_MOIIO2(val) (((val) & 0x3) << 20)
#define RPCIF_CMNCR_MOIIO1(val) (((val) & 0x3) << 18)
#define RPCIF_CMNCR_MOIIO0(val) (((val) & 0x3) << 16)
#define RPCIF_CMNCR_MOIIO(val) (RPCIF_CMNCR_MOIIO0(val) | RPCIF_CMNCR_MOIIO1(val) | \
RPCIF_CMNCR_MOIIO2(val) | RPCIF_CMNCR_MOIIO3(val))
#define RPCIF_CMNCR_IO3FV(val) (((val) & 0x3) << 14) /* documented for RZ/G2L */
#define RPCIF_CMNCR_IO2FV(val) (((val) & 0x3) << 12) /* documented for RZ/G2L */
#define RPCIF_CMNCR_IO0FV(val) (((val) & 0x3) << 8)
#define RPCIF_CMNCR_IOFV(val) (RPCIF_CMNCR_IO0FV(val) | RPCIF_CMNCR_IO2FV(val) | \
RPCIF_CMNCR_IO3FV(val))
#define RPCIF_CMNCR_BSZ(val) (((val) & 0x3) << 0)
#define RPCIF_SSLDR 0x0004 /* R/W */
#define RPCIF_SSLDR_SPNDL(d) (((d) & 0x7) << 16)
#define RPCIF_SSLDR_SLNDL(d) (((d) & 0x7) << 8)
#define RPCIF_SSLDR_SCKDL(d) (((d) & 0x7) << 0)
#define RPCIF_DRCR 0x000C /* R/W */
#define RPCIF_DRCR_SSLN BIT(24)
#define RPCIF_DRCR_RBURST(v) ((((v) - 1) & 0x1F) << 16)
#define RPCIF_DRCR_RCF BIT(9)
#define RPCIF_DRCR_RBE BIT(8)
#define RPCIF_DRCR_SSLE BIT(0)
#define RPCIF_DRCMR 0x0010 /* R/W */
#define RPCIF_DRCMR_CMD(c) (((c) & 0xFF) << 16)
#define RPCIF_DRCMR_OCMD(c) (((c) & 0xFF) << 0)
#define RPCIF_DREAR 0x0014 /* R/W */
#define RPCIF_DREAR_EAV(c) (((c) & 0xF) << 16)
#define RPCIF_DREAR_EAC(c) (((c) & 0x7) << 0)
#define RPCIF_DROPR 0x0018 /* R/W */
#define RPCIF_DRENR 0x001C /* R/W */
#define RPCIF_DRENR_CDB(o) (u32)((((o) & 0x3) << 30))
#define RPCIF_DRENR_OCDB(o) (((o) & 0x3) << 28)
#define RPCIF_DRENR_ADB(o) (((o) & 0x3) << 24)
#define RPCIF_DRENR_OPDB(o) (((o) & 0x3) << 20)
#define RPCIF_DRENR_DRDB(o) (((o) & 0x3) << 16)
#define RPCIF_DRENR_DME BIT(15)
#define RPCIF_DRENR_CDE BIT(14)
#define RPCIF_DRENR_OCDE BIT(12)
#define RPCIF_DRENR_ADE(v) (((v) & 0xF) << 8)
#define RPCIF_DRENR_OPDE(v) (((v) & 0xF) << 4)
#define RPCIF_SMCR 0x0020 /* R/W */
#define RPCIF_SMCR_SSLKP BIT(8)
#define RPCIF_SMCR_SPIRE BIT(2)
#define RPCIF_SMCR_SPIWE BIT(1)
#define RPCIF_SMCR_SPIE BIT(0)
#define RPCIF_SMCMR 0x0024 /* R/W */
#define RPCIF_SMCMR_CMD(c) (((c) & 0xFF) << 16)
#define RPCIF_SMCMR_OCMD(c) (((c) & 0xFF) << 0)
#define RPCIF_SMADR 0x0028 /* R/W */
#define RPCIF_SMOPR 0x002C /* R/W */
#define RPCIF_SMOPR_OPD3(o) (((o) & 0xFF) << 24)
#define RPCIF_SMOPR_OPD2(o) (((o) & 0xFF) << 16)
#define RPCIF_SMOPR_OPD1(o) (((o) & 0xFF) << 8)
#define RPCIF_SMOPR_OPD0(o) (((o) & 0xFF) << 0)
#define RPCIF_SMENR 0x0030 /* R/W */
#define RPCIF_SMENR_CDB(o) (((o) & 0x3) << 30)
#define RPCIF_SMENR_OCDB(o) (((o) & 0x3) << 28)
#define RPCIF_SMENR_ADB(o) (((o) & 0x3) << 24)
#define RPCIF_SMENR_OPDB(o) (((o) & 0x3) << 20)
#define RPCIF_SMENR_SPIDB(o) (((o) & 0x3) << 16)
#define RPCIF_SMENR_DME BIT(15)
#define RPCIF_SMENR_CDE BIT(14)
#define RPCIF_SMENR_OCDE BIT(12)
#define RPCIF_SMENR_ADE(v) (((v) & 0xF) << 8)
#define RPCIF_SMENR_OPDE(v) (((v) & 0xF) << 4)
#define RPCIF_SMENR_SPIDE(v) (((v) & 0xF) << 0)
#define RPCIF_SMRDR0 0x0038 /* R */
#define RPCIF_SMRDR1 0x003C /* R */
#define RPCIF_SMWDR0 0x0040 /* W */
#define RPCIF_SMWDR1 0x0044 /* W */
#define RPCIF_CMNSR 0x0048 /* R */
#define RPCIF_CMNSR_SSLF BIT(1)
#define RPCIF_CMNSR_TEND BIT(0)
#define RPCIF_DRDMCR 0x0058 /* R/W */
#define RPCIF_DMDMCR_DMCYC(v) ((((v) - 1) & 0x1F) << 0)
#define RPCIF_DRDRENR 0x005C /* R/W */
#define RPCIF_DRDRENR_HYPE(v) (((v) & 0x7) << 12)
#define RPCIF_DRDRENR_ADDRE BIT(8)
#define RPCIF_DRDRENR_OPDRE BIT(4)
#define RPCIF_DRDRENR_DRDRE BIT(0)
#define RPCIF_SMDMCR 0x0060 /* R/W */
#define RPCIF_SMDMCR_DMCYC(v) ((((v) - 1) & 0x1F) << 0)
#define RPCIF_SMDRENR 0x0064 /* R/W */
#define RPCIF_SMDRENR_HYPE(v) (((v) & 0x7) << 12)
#define RPCIF_SMDRENR_ADDRE BIT(8)
#define RPCIF_SMDRENR_OPDRE BIT(4)
#define RPCIF_SMDRENR_SPIDRE BIT(0)
#define RPCIF_PHYADD 0x0070 /* R/W available on R-Car E3/D3/V3M and RZ/G2{E,L} */
#define RPCIF_PHYWR 0x0074 /* R/W available on R-Car E3/D3/V3M and RZ/G2{E,L} */
#define RPCIF_PHYCNT 0x007C /* R/W */
#define RPCIF_PHYCNT_CAL BIT(31)
#define RPCIF_PHYCNT_OCTA(v) (((v) & 0x3) << 22)
#define RPCIF_PHYCNT_EXDS BIT(21)
#define RPCIF_PHYCNT_OCT BIT(20)
#define RPCIF_PHYCNT_DDRCAL BIT(19)
#define RPCIF_PHYCNT_HS BIT(18)
#define RPCIF_PHYCNT_CKSEL(v) (((v) & 0x3) << 16) /* valid only for RZ/G2L */
#define RPCIF_PHYCNT_STRTIM(v) (((v) & 0x7) << 15 | ((v) & 0x8) << 24) /* valid for R-Car and RZ/G2{E,H,M,N} */
#define RPCIF_PHYCNT_WBUF2 BIT(4)
#define RPCIF_PHYCNT_WBUF BIT(2)
#define RPCIF_PHYCNT_PHYMEM(v) (((v) & 0x3) << 0)
#define RPCIF_PHYCNT_PHYMEM_MASK GENMASK(1, 0)
#define RPCIF_PHYOFFSET1 0x0080 /* R/W */
#define RPCIF_PHYOFFSET1_DDRTMG(v) (((v) & 0x3) << 28)
#define RPCIF_PHYOFFSET2 0x0084 /* R/W */
#define RPCIF_PHYOFFSET2_OCTTMG(v) (((v) & 0x7) << 8)
#define RPCIF_PHYINT 0x0088 /* R/W */
#define RPCIF_PHYINT_WPVAL BIT(1)
#include "renesas-rpc-if-regs.h"
#include "renesas-xspi-if-regs.h"
static const struct regmap_range rpcif_volatile_ranges[] = {
regmap_reg_range(RPCIF_SMRDR0, RPCIF_SMRDR1),
@@ -163,7 +32,31 @@ static const struct regmap_access_table rpcif_volatile_table = {
.n_yes_ranges = ARRAY_SIZE(rpcif_volatile_ranges),
};
static const struct regmap_range xspi_volatile_ranges[] = {
regmap_reg_range(XSPI_CDD0BUF0, XSPI_CDD0BUF0),
};
static const struct regmap_access_table xspi_volatile_table = {
.yes_ranges = xspi_volatile_ranges,
.n_yes_ranges = ARRAY_SIZE(xspi_volatile_ranges),
};
struct rpcif_priv;
struct rpcif_impl {
int (*hw_init)(struct rpcif_priv *rpc, bool hyperflash);
void (*prepare)(struct rpcif_priv *rpc, const struct rpcif_op *op,
u64 *offs, size_t *len);
int (*manual_xfer)(struct rpcif_priv *rpc);
size_t (*dirmap_read)(struct rpcif_priv *rpc, u64 offs, size_t len,
void *buf);
u32 status_reg;
u32 status_mask;
};
struct rpcif_info {
const struct regmap_config *regmap_config;
const struct rpcif_impl *impl;
enum rpcif_type type;
u8 strtim;
};
@@ -180,6 +73,8 @@ struct rpcif_priv {
enum rpcif_data_dir dir;
u8 bus_size;
u8 xfer_size;
u8 addr_nbytes; /* Specified for xSPI */
u32 proto; /* Specified for xSPI */
void *buffer;
u32 xferlen;
u32 smcr;
@@ -191,26 +86,6 @@ struct rpcif_priv {
u32 ddr; /* DRDRENR or SMDRENR */
};
static const struct rpcif_info rpcif_info_r8a7796 = {
.type = RPCIF_RCAR_GEN3,
.strtim = 6,
};
static const struct rpcif_info rpcif_info_gen3 = {
.type = RPCIF_RCAR_GEN3,
.strtim = 7,
};
static const struct rpcif_info rpcif_info_rz_g2l = {
.type = RPCIF_RZ_G2L,
.strtim = 7,
};
static const struct rpcif_info rpcif_info_gen4 = {
.type = RPCIF_RCAR_GEN4,
.strtim = 15,
};
/*
* Custom accessor functions to ensure SM[RW]DR[01] are always accessed with
* proper width. Requires rpcif_priv.xfer_size to be correctly set before!
@@ -300,6 +175,33 @@ static const struct regmap_config rpcif_regmap_config = {
.volatile_table = &rpcif_volatile_table,
};
static int xspi_reg_read(void *context, unsigned int reg, unsigned int *val)
{
struct rpcif_priv *xspi = context;
*val = readl(xspi->base + reg);
return 0;
}
static int xspi_reg_write(void *context, unsigned int reg, unsigned int val)
{
struct rpcif_priv *xspi = context;
writel(val, xspi->base + reg);
return 0;
}
static const struct regmap_config xspi_regmap_config = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
.reg_read = xspi_reg_read,
.reg_write = xspi_reg_write,
.fast_io = true,
.max_register = XSPI_INTE,
.volatile_table = &xspi_volatile_table,
};
int rpcif_sw_init(struct rpcif *rpcif, struct device *dev)
{
struct rpcif_priv *rpc = dev_get_drvdata(dev);
@@ -307,6 +209,7 @@ int rpcif_sw_init(struct rpcif *rpcif, struct device *dev)
rpcif->dev = dev;
rpcif->dirmap = rpc->dirmap;
rpcif->size = rpc->size;
rpcif->xspi = rpc->info->type == XSPI_RZ_G3E;
return 0;
}
EXPORT_SYMBOL(rpcif_sw_init);
@@ -325,16 +228,11 @@ static void rpcif_rzg2l_timing_adjust_sdr(struct rpcif_priv *rpc)
regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000032);
}
int rpcif_hw_init(struct device *dev, bool hyperflash)
static int rpcif_hw_init_impl(struct rpcif_priv *rpc, bool hyperflash)
{
struct rpcif_priv *rpc = dev_get_drvdata(dev);
u32 dummy;
int ret;
ret = pm_runtime_resume_and_get(dev);
if (ret)
return ret;
if (rpc->info->type == RPCIF_RZ_G2L) {
ret = reset_control_reset(rpc->rstc);
if (ret)
@@ -382,21 +280,62 @@ int rpcif_hw_init(struct device *dev, bool hyperflash)
regmap_write(rpc->regmap, RPCIF_SSLDR, RPCIF_SSLDR_SPNDL(7) |
RPCIF_SSLDR_SLNDL(7) | RPCIF_SSLDR_SCKDL(7));
pm_runtime_put(dev);
rpc->bus_size = hyperflash ? 2 : 1;
return 0;
}
static int xspi_hw_init_impl(struct rpcif_priv *xspi, bool hyperflash)
{
int ret;
ret = reset_control_reset(xspi->rstc);
if (ret)
return ret;
regmap_write(xspi->regmap, XSPI_WRAPCFG, 0x0);
regmap_update_bits(xspi->regmap, XSPI_LIOCFGCS0,
XSPI_LIOCFG_PRTMD(0x3ff) | XSPI_LIOCFG_CSMIN(0xf) |
XSPI_LIOCFG_CSASTEX | XSPI_LIOCFG_CSNEGEX,
XSPI_LIOCFG_PRTMD(0) | XSPI_LIOCFG_CSMIN(0) |
XSPI_LIOCFG_CSASTEX | XSPI_LIOCFG_CSNEGEX);
regmap_update_bits(xspi->regmap, XSPI_CCCTL0CS0, XSPI_CCCTL0_CAEN, 0);
regmap_update_bits(xspi->regmap, XSPI_CDCTL0,
XSPI_CDCTL0_TRREQ | XSPI_CDCTL0_CSSEL, 0);
regmap_update_bits(xspi->regmap, XSPI_INTE, XSPI_INTE_CMDCMPE,
XSPI_INTE_CMDCMPE);
return 0;
}
int rpcif_hw_init(struct device *dev, bool hyperflash)
{
struct rpcif_priv *rpc = dev_get_drvdata(dev);
int ret;
ret = pm_runtime_resume_and_get(dev);
if (ret)
return ret;
ret = rpc->info->impl->hw_init(rpc, hyperflash);
pm_runtime_put(dev);
return ret;
}
EXPORT_SYMBOL(rpcif_hw_init);
static int wait_msg_xfer_end(struct rpcif_priv *rpc)
{
u32 sts;
return regmap_read_poll_timeout(rpc->regmap, RPCIF_CMNSR, sts,
sts & RPCIF_CMNSR_TEND, 0,
USEC_PER_SEC);
return regmap_read_poll_timeout(rpc->regmap, rpc->info->impl->status_reg,
sts, sts & rpc->info->impl->status_mask,
0, USEC_PER_SEC);
}
static u8 rpcif_bits_set(struct rpcif_priv *rpc, u32 nbytes)
@@ -412,11 +351,9 @@ static u8 rpcif_bit_size(u8 buswidth)
return buswidth > 4 ? 2 : ilog2(buswidth);
}
void rpcif_prepare(struct device *dev, const struct rpcif_op *op, u64 *offs,
size_t *len)
static void rpcif_prepare_impl(struct rpcif_priv *rpc, const struct rpcif_op *op,
u64 *offs, size_t *len)
{
struct rpcif_priv *rpc = dev_get_drvdata(dev);
rpc->smcr = 0;
rpc->smadr = 0;
rpc->enable = 0;
@@ -497,18 +434,76 @@ void rpcif_prepare(struct device *dev, const struct rpcif_op *op, u64 *offs,
rpc->enable |= RPCIF_SMENR_SPIDB(rpcif_bit_size(op->data.buswidth));
}
}
EXPORT_SYMBOL(rpcif_prepare);
int rpcif_manual_xfer(struct device *dev)
static void xspi_prepare_impl(struct rpcif_priv *xspi, const struct rpcif_op *op,
u64 *offs, size_t *len)
{
xspi->smadr = 0;
xspi->addr_nbytes = 0;
xspi->command = 0;
xspi->option = 0;
xspi->dummy = 0;
xspi->xferlen = 0;
xspi->proto = 0;
if (op->cmd.buswidth)
xspi->command = op->cmd.opcode;
if (op->ocmd.buswidth)
xspi->command = (xspi->command << 8) | op->ocmd.opcode;
if (op->addr.buswidth) {
xspi->addr_nbytes = op->addr.nbytes;
if (offs && len)
xspi->smadr = *offs;
else
xspi->smadr = op->addr.val;
}
if (op->dummy.buswidth)
xspi->dummy = op->dummy.ncycles;
xspi->dir = op->data.dir;
if (op->data.buswidth) {
u32 nbytes;
xspi->buffer = op->data.buf.in;
if (offs && len)
nbytes = *len;
else
nbytes = op->data.nbytes;
xspi->xferlen = nbytes;
}
if (op->cmd.buswidth == 1) {
if (op->addr.buswidth == 2 || op->data.buswidth == 2)
xspi->proto = PROTO_1S_2S_2S;
else if (op->addr.buswidth == 4 || op->data.buswidth == 4)
xspi->proto = PROTO_1S_4S_4S;
} else if (op->cmd.buswidth == 2 &&
(op->addr.buswidth == 2 || op->data.buswidth == 2)) {
xspi->proto = PROTO_2S_2S_2S;
} else if (op->cmd.buswidth == 4 &&
(op->addr.buswidth == 4 || op->data.buswidth == 4)) {
xspi->proto = PROTO_4S_4S_4S;
}
}
void rpcif_prepare(struct device *dev, const struct rpcif_op *op, u64 *offs,
size_t *len)
{
struct rpcif_priv *rpc = dev_get_drvdata(dev);
rpc->info->impl->prepare(rpc, op, offs, len);
}
EXPORT_SYMBOL(rpcif_prepare);
static int rpcif_manual_xfer_impl(struct rpcif_priv *rpc)
{
u32 smenr, smcr, pos = 0, max = rpc->bus_size == 2 ? 8 : 4;
int ret = 0;
ret = pm_runtime_resume_and_get(dev);
if (ret < 0)
return ret;
regmap_update_bits(rpc->regmap, RPCIF_PHYCNT,
RPCIF_PHYCNT_CAL, RPCIF_PHYCNT_CAL);
regmap_update_bits(rpc->regmap, RPCIF_CMNCR,
@@ -616,15 +611,169 @@ int rpcif_manual_xfer(struct device *dev)
goto err_out;
}
exit:
pm_runtime_put(dev);
return ret;
err_out:
if (reset_control_reset(rpc->rstc))
dev_err(dev, "Failed to reset HW\n");
rpcif_hw_init(dev, rpc->bus_size == 2);
goto exit;
dev_err(rpc->dev, "Failed to reset HW\n");
rpcif_hw_init_impl(rpc, rpc->bus_size == 2);
return ret;
}
static int xspi_manual_xfer_impl(struct rpcif_priv *xspi)
{
u32 pos = 0, max = 8;
int ret = 0;
regmap_update_bits(xspi->regmap, XSPI_CDCTL0, XSPI_CDCTL0_TRNUM(0x3),
XSPI_CDCTL0_TRNUM(0));
regmap_update_bits(xspi->regmap, XSPI_CDCTL0, XSPI_CDCTL0_TRREQ, 0);
regmap_write(xspi->regmap, XSPI_CDTBUF0,
XSPI_CDTBUF_CMDSIZE(0x1) | XSPI_CDTBUF_CMD_FIELD(xspi->command));
regmap_write(xspi->regmap, XSPI_CDABUF0, 0);
regmap_update_bits(xspi->regmap, XSPI_CDTBUF0, XSPI_CDTBUF_ADDSIZE(0x7),
XSPI_CDTBUF_ADDSIZE(xspi->addr_nbytes));
regmap_write(xspi->regmap, XSPI_CDABUF0, xspi->smadr);
regmap_update_bits(xspi->regmap, XSPI_LIOCFGCS0, XSPI_LIOCFG_PRTMD(0x3ff),
XSPI_LIOCFG_PRTMD(xspi->proto));
switch (xspi->dir) {
case RPCIF_DATA_OUT:
while (pos < xspi->xferlen) {
u32 bytes_left = xspi->xferlen - pos;
u32 nbytes, data[2], *p = data;
regmap_update_bits(xspi->regmap, XSPI_CDTBUF0,
XSPI_CDTBUF_TRTYPE, XSPI_CDTBUF_TRTYPE);
nbytes = bytes_left >= max ? max : bytes_left;
regmap_update_bits(xspi->regmap, XSPI_CDTBUF0,
XSPI_CDTBUF_DATASIZE(0xf),
XSPI_CDTBUF_DATASIZE(nbytes));
regmap_update_bits(xspi->regmap, XSPI_CDTBUF0,
XSPI_CDTBUF_ADDSIZE(0x7),
XSPI_CDTBUF_ADDSIZE(xspi->addr_nbytes));
memcpy(data, xspi->buffer + pos, nbytes);
if (nbytes > 4) {
regmap_write(xspi->regmap, XSPI_CDD0BUF0, *p++);
regmap_write(xspi->regmap, XSPI_CDD1BUF0, *p);
} else {
regmap_write(xspi->regmap, XSPI_CDD0BUF0, *p);
}
regmap_write(xspi->regmap, XSPI_CDABUF0, xspi->smadr + pos);
regmap_update_bits(xspi->regmap, XSPI_CDCTL0,
XSPI_CDCTL0_TRREQ, XSPI_CDCTL0_TRREQ);
ret = wait_msg_xfer_end(xspi);
if (ret)
goto err_out;
regmap_update_bits(xspi->regmap, XSPI_INTC,
XSPI_INTC_CMDCMPC, XSPI_INTC_CMDCMPC);
pos += nbytes;
}
regmap_update_bits(xspi->regmap, XSPI_CDCTL0, XSPI_CDCTL0_TRREQ, 0);
break;
case RPCIF_DATA_IN:
while (pos < xspi->xferlen) {
u32 bytes_left = xspi->xferlen - pos;
u32 nbytes, data[2], *p = data;
regmap_update_bits(xspi->regmap, XSPI_CDTBUF0,
XSPI_CDTBUF_TRTYPE,
~(u32)XSPI_CDTBUF_TRTYPE);
/* nbytes can be up to 8 bytes */
nbytes = bytes_left >= max ? max : bytes_left;
regmap_update_bits(xspi->regmap, XSPI_CDTBUF0,
XSPI_CDTBUF_DATASIZE(0xf),
XSPI_CDTBUF_DATASIZE(nbytes));
regmap_update_bits(xspi->regmap, XSPI_CDTBUF0,
XSPI_CDTBUF_ADDSIZE(0x7),
XSPI_CDTBUF_ADDSIZE(xspi->addr_nbytes));
if (xspi->addr_nbytes)
regmap_write(xspi->regmap, XSPI_CDABUF0,
xspi->smadr + pos);
regmap_update_bits(xspi->regmap, XSPI_CDTBUF0,
XSPI_CDTBUF_LATE(0x1f),
XSPI_CDTBUF_LATE(xspi->dummy));
regmap_update_bits(xspi->regmap, XSPI_CDCTL0,
XSPI_CDCTL0_TRREQ, XSPI_CDCTL0_TRREQ);
ret = wait_msg_xfer_end(xspi);
if (ret)
goto err_out;
if (nbytes > 4) {
regmap_read(xspi->regmap, XSPI_CDD0BUF0, p++);
regmap_read(xspi->regmap, XSPI_CDD1BUF0, p);
} else {
regmap_read(xspi->regmap, XSPI_CDD0BUF0, p);
}
memcpy(xspi->buffer + pos, data, nbytes);
regmap_update_bits(xspi->regmap, XSPI_INTC,
XSPI_INTC_CMDCMPC, XSPI_INTC_CMDCMPC);
pos += nbytes;
}
regmap_update_bits(xspi->regmap, XSPI_CDCTL0,
XSPI_CDCTL0_TRREQ, 0);
break;
default:
regmap_update_bits(xspi->regmap, XSPI_CDTBUF0,
XSPI_CDTBUF_TRTYPE, XSPI_CDTBUF_TRTYPE);
regmap_update_bits(xspi->regmap, XSPI_CDCTL0,
XSPI_CDCTL0_TRREQ, XSPI_CDCTL0_TRREQ);
ret = wait_msg_xfer_end(xspi);
if (ret)
goto err_out;
regmap_update_bits(xspi->regmap, XSPI_INTC,
XSPI_INTC_CMDCMPC, XSPI_INTC_CMDCMPC);
}
return ret;
err_out:
xspi_hw_init_impl(xspi, false);
return ret;
}
int rpcif_manual_xfer(struct device *dev)
{
struct rpcif_priv *rpc = dev_get_drvdata(dev);
int ret;
ret = pm_runtime_resume_and_get(dev);
if (ret)
return ret;
ret = rpc->info->impl->manual_xfer(rpc);
pm_runtime_put(dev);
return ret;
}
EXPORT_SYMBOL(rpcif_manual_xfer);
@@ -670,20 +819,15 @@ static void memcpy_fromio_readw(void *to,
}
}
ssize_t rpcif_dirmap_read(struct device *dev, u64 offs, size_t len, void *buf)
static size_t rpcif_dirmap_read_impl(struct rpcif_priv *rpc, u64 offs,
size_t len, void *buf)
{
struct rpcif_priv *rpc = dev_get_drvdata(dev);
loff_t from = offs & (rpc->size - 1);
size_t size = rpc->size - from;
int ret;
if (len > size)
len = size;
ret = pm_runtime_resume_and_get(dev);
if (ret < 0)
return ret;
regmap_update_bits(rpc->regmap, RPCIF_CMNCR, RPCIF_CMNCR_MD, 0);
regmap_write(rpc->regmap, RPCIF_DRCR, 0);
regmap_write(rpc->regmap, RPCIF_DRCMR, rpc->command);
@@ -700,12 +844,129 @@ ssize_t rpcif_dirmap_read(struct device *dev, u64 offs, size_t len, void *buf)
else
memcpy_fromio(buf, rpc->dirmap + from, len);
pm_runtime_put(dev);
return len;
}
static size_t xspi_dirmap_read_impl(struct rpcif_priv *xspi, u64 offs,
size_t len, void *buf)
{
loff_t from = offs & (xspi->size - 1);
size_t size = xspi->size - from;
u8 addsize = xspi->addr_nbytes - 1;
if (len > size)
len = size;
regmap_update_bits(xspi->regmap, XSPI_CMCFG0CS0,
XSPI_CMCFG0_FFMT(0x3) | XSPI_CMCFG0_ADDSIZE(0x3),
XSPI_CMCFG0_FFMT(0) | XSPI_CMCFG0_ADDSIZE(addsize));
regmap_update_bits(xspi->regmap, XSPI_CMCFG1CS0,
XSPI_CMCFG1_RDCMD(0xffff) | XSPI_CMCFG1_RDLATE(0x1f),
XSPI_CMCFG1_RDCMD_UPPER_BYTE(xspi->command) |
XSPI_CMCFG1_RDLATE(xspi->dummy));
regmap_update_bits(xspi->regmap, XSPI_BMCTL0, XSPI_BMCTL0_CS0ACC(0xff),
XSPI_BMCTL0_CS0ACC(0x01));
regmap_update_bits(xspi->regmap, XSPI_BMCFG,
XSPI_BMCFG_WRMD | XSPI_BMCFG_MWRCOMB |
XSPI_BMCFG_MWRSIZE(0xff) | XSPI_BMCFG_PREEN,
0 | XSPI_BMCFG_MWRCOMB | XSPI_BMCFG_MWRSIZE(0x0f) |
XSPI_BMCFG_PREEN);
regmap_update_bits(xspi->regmap, XSPI_LIOCFGCS0, XSPI_LIOCFG_PRTMD(0x3ff),
XSPI_LIOCFG_PRTMD(xspi->proto));
memcpy_fromio(buf, xspi->dirmap + from, len);
return len;
}
ssize_t rpcif_dirmap_read(struct device *dev, u64 offs, size_t len, void *buf)
{
struct rpcif_priv *rpc = dev_get_drvdata(dev);
size_t read;
int ret;
ret = pm_runtime_resume_and_get(dev);
if (ret)
return ret;
read = rpc->info->impl->dirmap_read(rpc, offs, len, buf);
pm_runtime_put(dev);
return read;
}
EXPORT_SYMBOL(rpcif_dirmap_read);
/**
* xspi_dirmap_write - Write data to xspi memory.
* @dev: xspi device
* @offs: offset
* @len: Number of bytes to be written.
* @buf: Buffer holding write data.
*
* This function writes data into xspi memory.
*
* Returns number of bytes written on success, else negative errno.
*/
ssize_t xspi_dirmap_write(struct device *dev, u64 offs, size_t len, const void *buf)
{
struct rpcif_priv *xspi = dev_get_drvdata(dev);
loff_t from = offs & (xspi->size - 1);
u8 addsize = xspi->addr_nbytes - 1;
size_t size = xspi->size - from;
ssize_t writebytes;
int ret;
ret = pm_runtime_resume_and_get(dev);
if (ret)
return ret;
if (len > size)
len = size;
if (len > MWRSIZE_MAX)
writebytes = MWRSIZE_MAX;
else
writebytes = len;
regmap_update_bits(xspi->regmap, XSPI_CMCFG0CS0,
XSPI_CMCFG0_FFMT(0x3) | XSPI_CMCFG0_ADDSIZE(0x3),
XSPI_CMCFG0_FFMT(0) | XSPI_CMCFG0_ADDSIZE(addsize));
regmap_update_bits(xspi->regmap, XSPI_CMCFG2CS0,
XSPI_CMCFG2_WRCMD_UPPER(0xff) | XSPI_CMCFG2_WRLATE(0x1f),
XSPI_CMCFG2_WRCMD_UPPER(xspi->command) |
XSPI_CMCFG2_WRLATE(xspi->dummy));
regmap_update_bits(xspi->regmap, XSPI_BMCTL0,
XSPI_BMCTL0_CS0ACC(0xff), XSPI_BMCTL0_CS0ACC(0x03));
regmap_update_bits(xspi->regmap, XSPI_BMCFG,
XSPI_BMCFG_WRMD | XSPI_BMCFG_MWRCOMB |
XSPI_BMCFG_MWRSIZE(0xff) | XSPI_BMCFG_PREEN,
0 | XSPI_BMCFG_MWRCOMB | XSPI_BMCFG_MWRSIZE(0x0f) |
XSPI_BMCFG_PREEN);
regmap_update_bits(xspi->regmap, XSPI_LIOCFGCS0, XSPI_LIOCFG_PRTMD(0x3ff),
XSPI_LIOCFG_PRTMD(xspi->proto));
memcpy_toio(xspi->dirmap + from, buf, writebytes);
/* Request to push the pending data */
if (writebytes < MWRSIZE_MAX)
regmap_update_bits(xspi->regmap, XSPI_BMCTL1,
XSPI_BMCTL1_MWRPUSH, XSPI_BMCTL1_MWRPUSH);
pm_runtime_put(dev);
return writebytes;
}
EXPORT_SYMBOL_GPL(xspi_dirmap_write);
static int rpcif_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
@@ -740,8 +1001,8 @@ static int rpcif_probe(struct platform_device *pdev)
rpc->base = devm_platform_ioremap_resource_byname(pdev, "regs");
if (IS_ERR(rpc->base))
return PTR_ERR(rpc->base);
rpc->regmap = devm_regmap_init(dev, NULL, rpc, &rpcif_regmap_config);
rpc->info = of_device_get_match_data(dev);
rpc->regmap = devm_regmap_init(dev, NULL, rpc, rpc->info->regmap_config);
if (IS_ERR(rpc->regmap)) {
dev_err(dev, "failed to init regmap for rpcif, error %ld\n",
PTR_ERR(rpc->regmap));
@@ -754,11 +1015,29 @@ static int rpcif_probe(struct platform_device *pdev)
return PTR_ERR(rpc->dirmap);
rpc->size = resource_size(res);
rpc->info = of_device_get_match_data(dev);
rpc->rstc = devm_reset_control_get_exclusive(dev, NULL);
rpc->rstc = devm_reset_control_array_get_exclusive(dev);
if (IS_ERR(rpc->rstc))
return PTR_ERR(rpc->rstc);
/*
* The enabling/disabling of spi/spix2 clocks at runtime leading to
* flash write failure. So, enable these clocks during probe() and
* disable it in remove().
*/
if (rpc->info->type == XSPI_RZ_G3E) {
struct clk *spi_clk;
spi_clk = devm_clk_get_enabled(dev, "spix2");
if (IS_ERR(spi_clk))
return dev_err_probe(dev, PTR_ERR(spi_clk),
"cannot get enabled spix2 clk\n");
spi_clk = devm_clk_get_enabled(dev, "spi");
if (IS_ERR(spi_clk))
return dev_err_probe(dev, PTR_ERR(spi_clk),
"cannot get enabled spi clk\n");
}
vdev = platform_device_alloc(name, pdev->id);
if (!vdev)
return -ENOMEM;
@@ -784,8 +1063,61 @@ static void rpcif_remove(struct platform_device *pdev)
platform_device_unregister(rpc->vdev);
}
static const struct rpcif_impl rpcif_impl = {
.hw_init = rpcif_hw_init_impl,
.prepare = rpcif_prepare_impl,
.manual_xfer = rpcif_manual_xfer_impl,
.dirmap_read = rpcif_dirmap_read_impl,
.status_reg = RPCIF_CMNSR,
.status_mask = RPCIF_CMNSR_TEND,
};
static const struct rpcif_impl xspi_impl = {
.hw_init = xspi_hw_init_impl,
.prepare = xspi_prepare_impl,
.manual_xfer = xspi_manual_xfer_impl,
.dirmap_read = xspi_dirmap_read_impl,
.status_reg = XSPI_INTS,
.status_mask = XSPI_INTS_CMDCMP,
};
static const struct rpcif_info rpcif_info_r8a7796 = {
.regmap_config = &rpcif_regmap_config,
.impl = &rpcif_impl,
.type = RPCIF_RCAR_GEN3,
.strtim = 6,
};
static const struct rpcif_info rpcif_info_gen3 = {
.regmap_config = &rpcif_regmap_config,
.impl = &rpcif_impl,
.type = RPCIF_RCAR_GEN3,
.strtim = 7,
};
static const struct rpcif_info rpcif_info_rz_g2l = {
.regmap_config = &rpcif_regmap_config,
.impl = &rpcif_impl,
.type = RPCIF_RZ_G2L,
.strtim = 7,
};
static const struct rpcif_info rpcif_info_gen4 = {
.regmap_config = &rpcif_regmap_config,
.impl = &rpcif_impl,
.type = RPCIF_RCAR_GEN4,
.strtim = 15,
};
static const struct rpcif_info xspi_info_r9a09g047 = {
.regmap_config = &xspi_regmap_config,
.impl = &xspi_impl,
.type = XSPI_RZ_G3E,
};
static const struct of_device_id rpcif_of_match[] = {
{ .compatible = "renesas,r8a7796-rpc-if", .data = &rpcif_info_r8a7796 },
{ .compatible = "renesas,r9a09g047-xspi", .data = &xspi_info_r9a09g047 },
{ .compatible = "renesas,rcar-gen3-rpc-if", .data = &rpcif_info_gen3 },
{ .compatible = "renesas,rcar-gen4-rpc-if", .data = &rpcif_info_gen4 },
{ .compatible = "renesas,rzg2l-rpc-if", .data = &rpcif_info_rz_g2l },

105
drivers/memory/renesas-xspi-if-regs.h Normal file
View File

@@ -0,0 +1,105 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* RZ xSPI Interface Registers Definitions
*
* Copyright (C) 2025 Renesas Electronics Corporation
*/
#ifndef __RENESAS_XSPI_IF_REGS_H__
#define __RENESAS_XSPI_IF_REGS_H__
#include <linux/bits.h>
/* xSPI Wrapper Configuration Register */
#define XSPI_WRAPCFG 0x0000
/* xSPI Bridge Configuration Register */
#define XSPI_BMCFG 0x0008
#define XSPI_BMCFG_WRMD BIT(0)
#define XSPI_BMCFG_MWRCOMB BIT(7)
#define XSPI_BMCFG_MWRSIZE(val) (((val) & 0xff) << 8)
#define XSPI_BMCFG_PREEN BIT(16)
/* xSPI Command Map Configuration Register 0 CS0 */
#define XSPI_CMCFG0CS0 0x0010
#define XSPI_CMCFG0_FFMT(val) (((val) & 0x03) << 0)
#define XSPI_CMCFG0_ADDSIZE(val) (((val) & 0x03) << 2)
/* xSPI Command Map Configuration Register 1 CS0 */
#define XSPI_CMCFG1CS0 0x0014
#define XSPI_CMCFG1_RDCMD(val) (((val) & 0xffff) << 0)
#define XSPI_CMCFG1_RDCMD_UPPER_BYTE(val) (((val) & 0xff) << 8)
#define XSPI_CMCFG1_RDLATE(val) (((val) & 0x1f) << 16)
/* xSPI Command Map Configuration Register 2 CS0 */
#define XSPI_CMCFG2CS0 0x0018
#define XSPI_CMCFG2_WRCMD(val) (((val) & 0xffff) << 0)
#define XSPI_CMCFG2_WRCMD_UPPER(val) (((val) & 0xff) << 8)
#define XSPI_CMCFG2_WRLATE(val) (((val) & 0x1f) << 16)
/* xSPI Link I/O Configuration Register CS0 */
#define XSPI_LIOCFGCS0 0x0050
#define XSPI_LIOCFG_PRTMD(val) (((val) & 0x3ff) << 0)
#define XSPI_LIOCFG_CSMIN(val) (((val) & 0x0f) << 16)
#define XSPI_LIOCFG_CSASTEX BIT(20)
#define XSPI_LIOCFG_CSNEGEX BIT(21)
/* xSPI Bridge Map Control Register 0 */
#define XSPI_BMCTL0 0x0060
#define XSPI_BMCTL0_CS0ACC(val) (((val) & 0x03) << 0)
/* xSPI Bridge Map Control Register 1 */
#define XSPI_BMCTL1 0x0064
#define XSPI_BMCTL1_MWRPUSH BIT(8)
/* xSPI Command Manual Control Register 0 */
#define XSPI_CDCTL0 0x0070
#define XSPI_CDCTL0_TRREQ BIT(0)
#define XSPI_CDCTL0_CSSEL BIT(3)
#define XSPI_CDCTL0_TRNUM(val) (((val) & 0x03) << 4)
/* xSPI Command Manual Type Buf */
#define XSPI_CDTBUF0 0x0080
#define XSPI_CDTBUF_CMDSIZE(val) (((val) & 0x03) << 0)
#define XSPI_CDTBUF_ADDSIZE(val) (((val) & 0x07) << 2)
#define XSPI_CDTBUF_DATASIZE(val) (((val) & 0x0f) << 5)
#define XSPI_CDTBUF_LATE(val) (((val) & 0x1f) << 9)
#define XSPI_CDTBUF_TRTYPE BIT(15)
#define XSPI_CDTBUF_CMD(val) (((val) & 0xffff) << 16)
#define XSPI_CDTBUF_CMD_FIELD(val) (((val) & 0xff) << 24)
/* xSPI Command Manual Address Buff */
#define XSPI_CDABUF0 0x0084
/* xSPI Command Manual Data 0 Buf */
#define XSPI_CDD0BUF0 0x0088
/* xSPI Command Manual Data 1 Buf */
#define XSPI_CDD1BUF0 0x008c
/* xSPI Command Calibration Control Register 0 CS0 */
#define XSPI_CCCTL0CS0 0x0130
#define XSPI_CCCTL0_CAEN BIT(0)
/* xSPI Interrupt Status Register */
#define XSPI_INTS 0x0190
#define XSPI_INTS_CMDCMP BIT(0)
/* xSPI Interrupt Clear Register */
#define XSPI_INTC 0x0194
#define XSPI_INTC_CMDCMPC BIT(0)
/* xSPI Interrupt Enable Register */
#define XSPI_INTE 0x0198
#define XSPI_INTE_CMDCMPE BIT(0)
/* Maximum data size of MWRSIZE*/
#define MWRSIZE_MAX 64
/* xSPI Protocol mode */
#define PROTO_1S_2S_2S 0x48
#define PROTO_2S_2S_2S 0x49
#define PROTO_1S_4S_4S 0x090
#define PROTO_4S_4S_4S 0x092
#endif /* __RENESAS_XSPI_IF_REGS_H__ */

4
include/memory/renesas-rpc-if.h
View File

@@ -61,12 +61,14 @@ enum rpcif_type {
RPCIF_RCAR_GEN3,
RPCIF_RCAR_GEN4,
RPCIF_RZ_G2L,
XSPI_RZ_G3E,
};
struct rpcif {
struct device *dev;
void __iomem *dirmap;
size_t size;
bool xspi;
};
int rpcif_sw_init(struct rpcif *rpc, struct device *dev);
@@ -75,5 +77,7 @@ void rpcif_prepare(struct device *dev, const struct rpcif_op *op, u64 *offs,
size_t *len);
int rpcif_manual_xfer(struct device *dev);
ssize_t rpcif_dirmap_read(struct device *dev, u64 offs, size_t len, void *buf);
ssize_t xspi_dirmap_write(struct device *dev, u64 offs, size_t len,
const void *buf);
#endif // __RENESAS_RPC_IF_H