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drm/amd/display: Disable SubVP for PSR panels

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[Description]
- We cannot enable subvp on PSR panels because when
  PSR is active, HUBP is turned off and we cannot rely
  on the HUBP vline interrupt
- When in PSR, surface data also cannot be prefetched to MALL
  because the main HUBP will be off

Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Reviewed-by: Nevenko Stupar <Nevenko.Stupar@amd.com>
Acked-by: Alan Liu <HaoPing.Liu@amd.com>
Signed-off-by: Alvin Lee <Alvin.Lee2@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Alvin Lee
2023-01-10 11:27:59 -05:00
committed by Alex Deucher
parent e019a7ba38
commit 9973364832
3 changed files with 12 additions and 1 deletions
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1
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.h
View File

@@ -122,6 +122,7 @@ bool dcn32_mpo_in_use(struct dc_state *context);
bool dcn32_any_surfaces_rotated(struct dc *dc, struct dc_state *context);
bool dcn32_is_center_timing(struct pipe_ctx *pipe);
bool dcn32_is_psr_capable(struct pipe_ctx *pipe);
struct pipe_ctx *dcn32_acquire_idle_pipe_for_head_pipe_in_layer(
struct dc_state *state,

10
drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource_helpers.c
View File

@@ -251,6 +251,16 @@ bool dcn32_is_center_timing(struct pipe_ctx *pipe)
return is_center_timing;
}
bool dcn32_is_psr_capable(struct pipe_ctx *pipe)
{
bool psr_capable = false;
if (pipe->stream && pipe->stream->link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED) {
psr_capable = true;
}
return psr_capable;
}
/**
* *******************************************************************************************
* dcn32_determine_det_override: Determine DET allocation for each pipe

2
drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
View File

@@ -692,7 +692,7 @@ static bool dcn32_assign_subvp_pipe(struct dc *dc,
* to combine this with SubVP can cause issues with the scheduling).
* - Not TMZ surface
*/
if (pipe->plane_state && !pipe->top_pipe && !dcn32_is_center_timing(pipe) &&
if (pipe->plane_state && !pipe->top_pipe && !dcn32_is_center_timing(pipe) && !dcn32_is_psr_capable(pipe) &&
pipe->stream->mall_stream_config.type == SUBVP_NONE && refresh_rate < 120 && !pipe->plane_state->address.tmz_surface &&
(vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] <= 0 ||
(vba->ActiveDRAMClockChangeLatencyMarginPerState[vba->VoltageLevel][vba->maxMpcComb][vba->pipe_plane[pipe_idx]] > 0 &&