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ASoC: fsl_mqs: Distinguish different modules by system manager indices

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On i.MX94, the MQS2 also needs to be configured by SCMI interface, add
sm_index variable in struct fsl_mqs_soc_data to distinguish the MQS1 and
MQS2 on this platform.

Add the system manager indices for i.MX94 in the header file.

Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Link: https://patch.msgid.link/20250620055229.965942-2-shengjiu.wang@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Shengjiu Wang
2025-06-20 13:52:28 +08:00
committed by Mark Brown
parent b27a58ecdf
commit 9931d2899e
2 changed files with 16 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
include/linux/firmware/imx/sm.h
View File

@@ -18,6 +18,14 @@
#define SCMI_IMX_CTRL_SAI4_MCLK 4 /* WAKE SAI4 MCLK */
#define SCMI_IMX_CTRL_SAI5_MCLK 5 /* WAKE SAI5 MCLK */
#define SCMI_IMX94_CTRL_PDM_CLK_SEL 0U /*!< AON PDM clock sel */
#define SCMI_IMX94_CTRL_MQS1_SETTINGS 1U /*!< AON MQS settings */
#define SCMI_IMX94_CTRL_MQS2_SETTINGS 2U /*!< WAKE MQS settings */
#define SCMI_IMX94_CTRL_SAI1_MCLK 3U /*!< AON SAI1 MCLK */
#define SCMI_IMX94_CTRL_SAI2_MCLK 4U /*!< WAKE SAI2 MCLK */
#define SCMI_IMX94_CTRL_SAI3_MCLK 5U /*!< WAKE SAI3 MCLK */
#define SCMI_IMX94_CTRL_SAI4_MCLK 6U /*!< WAKE SAI4 MCLK */
int scmi_imx_misc_ctrl_get(u32 id, u32 *num, u32 *val);
int scmi_imx_misc_ctrl_set(u32 id, u32 val);

11
sound/soc/fsl/fsl_mqs.c
View File

@@ -39,6 +39,7 @@ enum reg_type {
* struct fsl_mqs_soc_data - soc specific data
*
* @type: control register space type
* @sm_index: index from definition in system manager
* @ctrl_off: control register offset
* @en_mask: enable bit mask
* @en_shift: enable bit shift
@@ -51,6 +52,7 @@ enum reg_type {
*/
struct fsl_mqs_soc_data {
enum reg_type type;
int sm_index;
int ctrl_off;
int en_mask;
int en_shift;
@@ -82,7 +84,7 @@ static int fsl_mqs_sm_read(void *context, unsigned int reg, unsigned int *val)
if (IS_ENABLED(CONFIG_IMX_SCMI_MISC_DRV) &&
mqs_priv->soc->ctrl_off == reg)
return scmi_imx_misc_ctrl_get(SCMI_IMX_CTRL_MQS1_SETTINGS, &num, val);
return scmi_imx_misc_ctrl_get(mqs_priv->soc->sm_index, &num, val);
return -EINVAL;
};
@@ -93,7 +95,7 @@ static int fsl_mqs_sm_write(void *context, unsigned int reg, unsigned int val)
if (IS_ENABLED(CONFIG_IMX_SCMI_MISC_DRV) &&
mqs_priv->soc->ctrl_off == reg)
return scmi_imx_misc_ctrl_set(SCMI_IMX_CTRL_MQS1_SETTINGS, val);
return scmi_imx_misc_ctrl_set(mqs_priv->soc->sm_index, val);
return -EINVAL;
};
@@ -386,6 +388,7 @@ static const struct fsl_mqs_soc_data fsl_mqs_imx93_data = {
static const struct fsl_mqs_soc_data fsl_mqs_imx95_aon_data = {
.type = TYPE_REG_SM,
.sm_index = SCMI_IMX_CTRL_MQS1_SETTINGS,
.ctrl_off = 0x88,
.en_mask = BIT(1),
.en_shift = 1,
@@ -412,6 +415,7 @@ static const struct fsl_mqs_soc_data fsl_mqs_imx95_netc_data = {
static const struct fsl_mqs_soc_data fsl_mqs_imx943_aon_data = {
.type = TYPE_REG_SM,
.sm_index = SCMI_IMX94_CTRL_MQS1_SETTINGS,
.ctrl_off = 0x88,
.en_mask = BIT(1),
.en_shift = 1,
@@ -424,7 +428,8 @@ static const struct fsl_mqs_soc_data fsl_mqs_imx943_aon_data = {
};
static const struct fsl_mqs_soc_data fsl_mqs_imx943_wakeup_data = {
.type = TYPE_REG_GPR,
.type = TYPE_REG_SM,
.sm_index = SCMI_IMX94_CTRL_MQS2_SETTINGS,
.ctrl_off = 0x10,
.en_mask = BIT(1),
.en_shift = 1,