rtw89: correct CCA control

EDCCA signal can block transmitting in certain situation, so ignore this
signal and use others to decide transmitting time.

Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20220506120216.58567-4-pkshih@realtek.com
This commit is contained in:
Ping-Ke Shih
2022-05-06 20:02:14 +08:00
committed by Kalle Valo
parent 4b0d341b2e
commit 98ed6159a5

View File

@@ -1890,11 +1890,12 @@ static int cca_ctrl_init(struct rtw89_dev *rtwdev, u8 mac_idx)
B_AX_CTN_CHK_BASIC_NAV | B_AX_CTN_CHK_BTCCA |
B_AX_CTN_CHK_EDCCA | B_AX_CTN_CHK_CCA_S80 |
B_AX_CTN_CHK_CCA_S40 | B_AX_CTN_CHK_CCA_S20 |
B_AX_CTN_CHK_CCA_P20 | B_AX_SIFS_CHK_EDCCA);
B_AX_CTN_CHK_CCA_P20);
val &= ~(B_AX_TB_CHK_TX_NAV | B_AX_TB_CHK_CCA_S80 |
B_AX_TB_CHK_CCA_S40 | B_AX_TB_CHK_CCA_S20 |
B_AX_SIFS_CHK_CCA_S80 | B_AX_SIFS_CHK_CCA_S40 |
B_AX_SIFS_CHK_CCA_S20 | B_AX_CTN_CHK_TXNAV);
B_AX_SIFS_CHK_CCA_S20 | B_AX_CTN_CHK_TXNAV |
B_AX_SIFS_CHK_EDCCA);
rtw89_write32(rtwdev, reg, val);