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drm/msm/dpu: Add CWB entry to catalog for SM8650

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Add a new block for concurrent writeback mux to the SM8650 HW catalog

Signed-off-by: Esha Bharadwaj <quic_ebharadw@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Jessica Zhang <quic_jesszhan@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/629219/
Link: https://lore.kernel.org/r/20241216-concurrent-wb-v4-9-fe220297a7f0@quicinc.com
This commit is contained in:
Esha Bharadwaj
2024-12-16 16:43:20 -08:00
committed by Dmitry Baryshkov
parent 835d106204
commit 989412edae
2 changed files with 34 additions and 0 deletions
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21
drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_10_0_sm8650.h
View File

@@ -352,6 +352,25 @@ static const struct dpu_wb_cfg sm8650_wb[] = {
},
};
static const struct dpu_cwb_cfg sm8650_cwb[] = {
{
.name = "cwb_0", .id = CWB_0,
.base = 0x66200, .len = 0x8,
},
{
.name = "cwb_1", .id = CWB_1,
.base = 0x66600, .len = 0x8,
},
{
.name = "cwb_2", .id = CWB_2,
.base = 0x7E200, .len = 0x8,
},
{
.name = "cwb_3", .id = CWB_3,
.base = 0x7E600, .len = 0x8,
},
};
static const struct dpu_intf_cfg sm8650_intf[] = {
{
.name = "intf_0", .id = INTF_0,
@@ -449,6 +468,8 @@ const struct dpu_mdss_cfg dpu_sm8650_cfg = {
.merge_3d = sm8650_merge_3d,
.wb_count = ARRAY_SIZE(sm8650_wb),
.wb = sm8650_wb,
.cwb_count = ARRAY_SIZE(sm8650_cwb),
.cwb = sm8650_cwb,
.intf_count = ARRAY_SIZE(sm8650_intf),
.intf = sm8650_intf,
.vbif_count = ARRAY_SIZE(sm8650_vbif),

13
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
View File

@@ -613,6 +613,16 @@ struct dpu_wb_cfg {
enum dpu_clk_ctrl_type clk_ctrl;
};
/*
* struct dpu_cwb_cfg : MDP CWB mux instance info
* @id: enum identifying this block
* @base: register base offset to mdss
* @features bit mask identifying sub-blocks/features
*/
struct dpu_cwb_cfg {
DPU_HW_BLK_INFO;
};
/**
* struct dpu_vbif_dynamic_ot_cfg - dynamic OT setting
* @pps pixel per seconds
@@ -815,6 +825,9 @@ struct dpu_mdss_cfg {
u32 dspp_count;
const struct dpu_dspp_cfg *dspp;
u32 cwb_count;
const struct dpu_cwb_cfg *cwb;
/* Add additional block data structures here */
const struct dpu_perf_cfg *perf;