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arm64: dts: renesas: r9a09g047: Add pincontrol node

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Add pincontrol node to RZ/G3E ("R9A09G047") SoC DTSI.

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/20241216195325.164212-7-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Biju Das
2024-12-16 19:53:16 +00:00
committed by Geert Uytterhoeven
parent 6e526427fa
commit 987040d460
1 changed files with 13 additions and 0 deletions
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13
arch/arm64/boot/dts/renesas/r9a09g047.dtsi
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@@ -131,6 +131,19 @@ soc: soc {
#size-cells = <2>;
ranges;
pinctrl: pinctrl@10410000 {
compatible = "renesas,r9a09g047-pinctrl";
reg = <0 0x10410000 0 0x10000>;
clocks = <&cpg CPG_CORE R9A09G047_IOTOP_0_SHCLK>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinctrl 0 0 232>;
#interrupt-cells = <2>;
interrupt-controller;
power-domains = <&cpg>;
resets = <&cpg 0xa5>, <&cpg 0xa6>;
};
cpg: clock-controller@10420000 {
compatible = "renesas,r9a09g047-cpg";
reg = <0 0x10420000 0 0x10000>;