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Merge branch 'pci/controller/dwc-ultrarisc'
- Add UltraRISC DP1000 PCIe controller DT binding and driver (Jia Wang) * pci/controller/dwc-ultrarisc: PCI: ultrarisc: Add UltraRISC DP1000 PCIe Root Complex driver dt-bindings: PCI: Add UltraRISC DP1000 PCIe controller
This commit is contained in:
Bjorn Helgaas
@@ -0,0 +1,93 @@
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/ultrarisc,dp1000-pcie.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: UltraRISC DP1000 PCIe Host Controller
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description:
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UltraRISC DP1000 SoC PCIe host controller is based on the DesignWare PCIe IP.
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maintainers:
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- Xincheng Zhang <zhangxincheng@ultrarisc.com>
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- Jia Wang <wangjia@ultrarisc.com>
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allOf:
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- $ref: /schemas/pci/snps,dw-pcie.yaml#
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properties:
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compatible:
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const: ultrarisc,dp1000-pcie
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reg:
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items:
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- description: Data Bus Interface (DBI) registers.
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- description: PCIe configuration space region.
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reg-names:
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items:
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- const: dbi
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- const: config
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num-lanes:
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [4, 16]
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description: Number of lanes to use.
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interrupts:
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items:
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- description: MSI interrupt
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- description: Legacy INTA interrupt
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- description: Legacy INTB interrupt
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- description: Legacy INTC interrupt
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- description: Legacy INTD interrupt
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interrupt-names:
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items:
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- const: msi
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- const: inta
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- const: intb
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- const: intc
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- const: intd
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required:
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- compatible
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- reg
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- reg-names
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- interrupts
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- interrupt-names
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unevaluatedProperties: false
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examples:
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- |
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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pcie@21000000 {
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compatible = "ultrarisc,dp1000-pcie";
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reg = <0x0 0x21000000 0x0 0x01000000>,
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<0x0 0x4fff0000 0x0 0x00010000>;
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reg-names = "dbi", "config";
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ranges = <0x81000000 0x0 0x4fbf0000 0x0 0x4fbf0000 0x0 0x00400000>,
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<0x82000000 0x0 0x40000000 0x0 0x40000000 0x0 0x0fbf0000>,
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<0xc3000000 0x40 0x00000000 0x40 0x00000000 0xd 0x00000000>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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device_type = "pci";
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dma-coherent;
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bus-range = <0x0 0xff>;
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num-lanes = <16>;
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interrupt-parent = <&plic>;
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interrupts = <43>, <44>, <45>, <46>, <47>;
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interrupt-names = "msi", "inta", "intb", "intc", "intd";
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interrupt-map-mask = <0x0 0x0 0x0 0x7>;
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interrupt-map = <0x0 0x0 0x0 0x1 &plic 44>,
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<0x0 0x0 0x0 0x2 &plic 45>,
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<0x0 0x0 0x0 0x3 &plic 46>,
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<0x0 0x0 0x0 0x4 &plic 47>;
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};
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};
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@@ -20759,6 +20759,14 @@ S: Maintained
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F: Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml
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F: drivers/pci/controller/plda/pcie-starfive.c
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PCIE DRIVER FOR ULTRARISC DP1000
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M: Xincheng Zhang <zhangxincheng@ultrarisc.com>
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M: Jia Wang <wangjia@ultrarisc.com>
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L: linux-pci@vger.kernel.org
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S: Maintained
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F: Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml
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F: drivers/pci/controller/dwc/pcie-ultrarisc.c
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PCIE ENDPOINT DRIVER FOR QUALCOMM
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M: Manivannan Sadhasivam <mani@kernel.org>
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L: linux-pci@vger.kernel.org
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@@ -561,4 +561,17 @@ config PCIE_VISCONTI_HOST
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Say Y here if you want PCIe controller support on Toshiba Visconti SoC.
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This driver supports TMPV7708 SoC.
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config PCIE_ULTRARISC
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tristate "UltraRISC PCIe host controller"
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depends on ARCH_ULTRARISC || COMPILE_TEST
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select PCIE_DW_HOST
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select PCI_MSI
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default y if ARCH_ULTRARISC
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help
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Enables support for the PCIe controller in the UltraRISC SoC.
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This driver supports UR-DP1000 SoC.
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By default, this symbol is enabled when ARCH_ULTRARISC is active,
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requiring no further configuration on that platform.
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endmenu
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@@ -39,6 +39,7 @@ obj-$(CONFIG_PCIE_RCAR_GEN4) += pcie-rcar-gen4.o
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obj-$(CONFIG_PCIE_SPACEMIT_K1) += pcie-spacemit-k1.o
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obj-$(CONFIG_PCIE_STM32_HOST) += pcie-stm32.o
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obj-$(CONFIG_PCIE_STM32_EP) += pcie-stm32-ep.o
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obj-$(CONFIG_PCIE_ULTRARISC) += pcie-ultrarisc.o
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# The following drivers are for devices that use the generic ACPI
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# pci_root.c driver but don't support standard ECAM config access.
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@@ -72,6 +72,8 @@
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/* Synopsys-specific PCIe configuration registers */
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#define PCIE_PORT_FORCE 0x708
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/* Bit[7:0] LINK_NUM: Link Number. Not used for endpoint */
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#define PORT_LINK_NUM_MASK GENMASK(7, 0)
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#define PORT_FORCE_DO_DESKEW_FOR_SRIS BIT(23)
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#define PCIE_PORT_AFR 0x70C
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@@ -99,6 +101,28 @@
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#define PCIE_PORT_LANE_SKEW 0x714
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#define PORT_LANE_SKEW_INSERT_MASK GENMASK(23, 0)
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/*
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* PCIE_TIMER_CTRL_MAX_FUNC_NUM: Timer Control and Max Function Number
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* Register.
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*
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* This register holds the ack frequency, latency, replay, fast link
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* scaling timers, and max function number values.
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*
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* Bit[30:29] FAST_LINK_SCALING_FACTOR: Fast Link Timer Scaling Factor.
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* 0x0 (SF_1024): Scaling Factor is 1024 (1ms is 1us).
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* When the LTSSM is in Config or L12 Entry State, 1ms
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* timer is 2us, 2ms timer is 4us and 3ms timer is 6us.
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* 0x1 (SF_256): Scaling Factor is 256 (1ms is 4us)
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* 0x2 (SF_64): Scaling Factor is 64 (1ms is 16us)
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* 0x3 (SF_16): Scaling Factor is 16 (1ms is 64us)
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*/
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#define PCIE_TIMER_CTRL_MAX_FUNC_NUM 0x718
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#define PORT_FLT_SF_MASK GENMASK(30, 29)
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#define PORT_FLT_SF_VAL_1024 0x0
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#define PORT_FLT_SF_VAL_256 0x1
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#define PORT_FLT_SF_VAL_64 0x2
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#define PORT_FLT_SF_VAL_16 0x3
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#define PCIE_PORT_DEBUG0 0x728
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#define PORT_LOGIC_LTSSM_STATE_MASK 0x3f
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#define PORT_LOGIC_LTSSM_STATE_L0 0x11
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175
drivers/pci/controller/dwc/pcie-ultrarisc.c
Normal file
175
drivers/pci/controller/dwc/pcie-ultrarisc.c
Normal file
@@ -0,0 +1,175 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* DWC PCIe RC driver for UltraRISC SoCs
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*
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* Copyright (C) 2026 UltraRISC Technology (Shanghai) Co., Ltd.
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of_device.h>
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#include <linux/pci.h>
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#include <linux/platform_device.h>
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#include <linux/resource.h>
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#include "pcie-designware.h"
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#define PCIE_CUS_CORE 0x400000
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#define LTSSM_ENABLE BIT(7)
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#define FAST_LINK_MODE BIT(12)
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#define HOLD_PHY_RST BIT(14)
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#define L1SUB_DISABLE BIT(15)
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#define ULTRARISC_PCIE_COMP_TIMEOUT_65_210MS 0x6
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static struct pci_ops ultrarisc_pci_ops = {
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.map_bus = dw_pcie_own_conf_map_bus,
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.read = pci_generic_config_read32,
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.write = pci_generic_config_write32,
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};
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static int ultrarisc_pcie_host_init(struct dw_pcie_rp *pp)
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{
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struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
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struct pci_host_bridge *bridge = pp->bridge;
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u8 cap_exp;
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u32 val;
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bridge->ops = &ultrarisc_pci_ops;
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if (dw_pcie_link_up(pci))
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return 0;
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val = dw_pcie_readl_dbi(pci, PCIE_CUS_CORE);
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val &= ~FAST_LINK_MODE;
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dw_pcie_writel_dbi(pci, PCIE_CUS_CORE, val);
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val = dw_pcie_readl_dbi(pci, PCIE_TIMER_CTRL_MAX_FUNC_NUM);
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FIELD_MODIFY(PORT_FLT_SF_MASK, &val, PORT_FLT_SF_VAL_64);
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dw_pcie_writel_dbi(pci, PCIE_TIMER_CTRL_MAX_FUNC_NUM, val);
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cap_exp = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
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val = dw_pcie_readl_dbi(pci, cap_exp + PCI_EXP_LNKCTL2);
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FIELD_MODIFY(PCI_EXP_LNKCTL2_TLS, &val, PCI_EXP_LNKCTL2_TLS_16_0GT);
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dw_pcie_writel_dbi(pci, cap_exp + PCI_EXP_LNKCTL2, val);
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val = dw_pcie_readl_dbi(pci, PCIE_PORT_FORCE);
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FIELD_MODIFY(PORT_LINK_NUM_MASK, &val, 0);
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dw_pcie_writel_dbi(pci, PCIE_PORT_FORCE, val);
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val = dw_pcie_readl_dbi(pci, cap_exp + PCI_EXP_DEVCTL2);
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FIELD_MODIFY(PCI_EXP_DEVCTL2_COMP_TIMEOUT, &val,
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ULTRARISC_PCIE_COMP_TIMEOUT_65_210MS);
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dw_pcie_writel_dbi(pci, cap_exp + PCI_EXP_DEVCTL2, val);
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val = dw_pcie_readl_dbi(pci, PCIE_CUS_CORE);
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val &= ~(HOLD_PHY_RST | L1SUB_DISABLE);
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dw_pcie_writel_dbi(pci, PCIE_CUS_CORE, val);
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return 0;
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}
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static void ultrarisc_pcie_pme_turn_off(struct dw_pcie_rp *pp)
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{
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/*
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* DP1000 does not support sending PME_Turn_Off from the RC.
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* Keep this callback empty to skip the generic MSG TLP path.
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*/
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}
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static const struct dw_pcie_host_ops ultrarisc_pcie_host_ops = {
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.init = ultrarisc_pcie_host_init,
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.pme_turn_off = ultrarisc_pcie_pme_turn_off,
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};
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static int ultrarisc_pcie_start_link(struct dw_pcie *pci)
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{
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u32 val;
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val = dw_pcie_readl_dbi(pci, PCIE_CUS_CORE);
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val |= LTSSM_ENABLE;
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dw_pcie_writel_dbi(pci, PCIE_CUS_CORE, val);
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return 0;
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}
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static const struct dw_pcie_ops dw_pcie_ops = {
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.start_link = ultrarisc_pcie_start_link,
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};
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static int ultrarisc_pcie_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct dw_pcie_rp *pp;
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struct dw_pcie *pci;
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int ret;
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pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
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if (!pci)
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return -ENOMEM;
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pci->dev = dev;
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pci->ops = &dw_pcie_ops;
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/* Set a default value suitable for at most 16 in and 16 out windows */
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pci->atu_size = SZ_8K;
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pp = &pci->pp;
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platform_set_drvdata(pdev, pci);
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pp->num_vectors = MAX_MSI_IRQS;
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/* No L2/L3 Ready indication is available on this platform */
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pp->skip_l23_ready = true;
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pp->ops = &ultrarisc_pcie_host_ops;
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ret = dw_pcie_host_init(pp);
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if (ret) {
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dev_err(dev, "Failed to initialize host\n");
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return ret;
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}
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return 0;
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}
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static int ultrarisc_pcie_suspend_noirq(struct device *dev)
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{
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struct dw_pcie *pci = dev_get_drvdata(dev);
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return dw_pcie_suspend_noirq(pci);
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}
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static int ultrarisc_pcie_resume_noirq(struct device *dev)
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{
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struct dw_pcie *pci = dev_get_drvdata(dev);
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return dw_pcie_resume_noirq(pci);
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}
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static const struct dev_pm_ops ultrarisc_pcie_pm_ops = {
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NOIRQ_SYSTEM_SLEEP_PM_OPS(ultrarisc_pcie_suspend_noirq,
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ultrarisc_pcie_resume_noirq)
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};
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static const struct of_device_id ultrarisc_pcie_of_match[] = {
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{
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.compatible = "ultrarisc,dp1000-pcie",
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},
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{},
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};
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MODULE_DEVICE_TABLE(of, ultrarisc_pcie_of_match);
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static struct platform_driver ultrarisc_pcie_driver = {
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.driver = {
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.name = "ultrarisc-pcie",
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.of_match_table = ultrarisc_pcie_of_match,
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.suppress_bind_attrs = true,
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.pm = &ultrarisc_pcie_pm_ops,
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},
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.probe = ultrarisc_pcie_probe,
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};
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builtin_platform_driver(ultrarisc_pcie_driver);
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MODULE_DESCRIPTION("UltraRISC DP1000 DWC PCIe host controller");
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MODULE_LICENSE("GPL");
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