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arm64: dts: qcom: monaco: Complete SDHC definition

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Add the missing SDHC properties required to enable HS200, HS400,
and HS400 Enhanced Strobe modes, as supported by this controller.

Select the proper default pinctrls.

Signed-off-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260116214354.256878-2-loic.poulain@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
This commit is contained in:
Loic Poulain
2026-01-16 22:43:53 +01:00
committed by Bjorn Andersson
parent d44e0ab972
commit 978400b7a6
1 changed files with 10 additions and 0 deletions
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10
arch/arm64/boot/dts/qcom/monaco.dtsi
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@@ -4740,11 +4740,21 @@ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
interconnect-names = "sdhc-ddr",
"cpu-sdhc";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&sdc1_state_on>;
pinctrl-1 = <&sdc1_state_off>;
qcom,dll-config = <0x000f64ee>;
qcom,ddr-config = <0x80040868>;
bus-width = <8>;
supports-cqe;
dma-coherent;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
status = "disabled";
sdhc1_opp_table: opp-table {