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Merge tag 'v4.21-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt

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Powerdomain and QoS nodes for rk3066 and rk3188. A fix for a rock2
regulator name and referencing all cpus in the cooling maps instead
of only cpu0.

* tag 'v4.21-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  ARM: dts: rockchip: Add all CPUs in cooling maps
  ARM: dts: rockchip: Fix rk3288-rock2 vcc_flash name
  ARM: dts: rockchip: add rk3066/rk3188 power-domains
  ARM: dts: rockchip: add qos nodes found on rk3066 and rk3188
  dt-bindings: add power-domain header for RK3066 SoCs
  dt-bindings: add power-domain header for RK3188 SoCs

Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
2018-11-30 15:03:39 -08:00
parent 11c99479d4 99935bd4b5
commit 9733488310
9 changed files with 224 additions and 16 deletions
Download Patch File Download Diff File Expand all files Collapse all files

52
arch/arm/boot/dts/rk3066a.dtsi
View File

@@ -7,6 +7,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/clock/rk3066a-cru.h>
#include <dt-bindings/power/rk3066-power.h>
#include "rk3xxx.dtsi"
/ {
@@ -595,6 +596,7 @@ &gpu {
"ppmmu2",
"pp3",
"ppmmu3";
power-domains = <&power RK3066_PD_GPU>;
};
&i2c0 {
@@ -643,6 +645,56 @@ &emmc {
dma-names = "rx-tx";
};
&pmu {
power: power-controller {
compatible = "rockchip,rk3066-power-controller";
#power-domain-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
pd_vio@RK3066_PD_VIO {
reg = <RK3066_PD_VIO>;
clocks = <&cru ACLK_LCDC0>,
<&cru ACLK_LCDC1>,
<&cru DCLK_LCDC0>,
<&cru DCLK_LCDC1>,
<&cru HCLK_LCDC0>,
<&cru HCLK_LCDC1>,
<&cru SCLK_CIF1>,
<&cru ACLK_CIF1>,
<&cru HCLK_CIF1>,
<&cru SCLK_CIF0>,
<&cru ACLK_CIF0>,
<&cru HCLK_CIF0>,
<&cru ACLK_IPP>,
<&cru HCLK_IPP>,
<&cru ACLK_RGA>,
<&cru HCLK_RGA>;
pm_qos = <&qos_lcdc0>,
<&qos_lcdc1>,
<&qos_cif0>,
<&qos_cif1>,
<&qos_ipp>,
<&qos_rga>;
};
pd_video@RK3066_PD_VIDEO {
reg = <RK3066_PD_VIDEO>;
clocks = <&cru ACLK_VDPU>,
<&cru ACLK_VEPU>,
<&cru HCLK_VDPU>,
<&cru HCLK_VEPU>;
pm_qos = <&qos_vpu>;
};
pd_gpu@RK3066_PD_GPU {
reg = <RK3066_PD_GPU>;
clocks = <&cru ACLK_GPU>;
pm_qos = <&qos_gpu>;
};
};
};
&pwm0 {
pinctrl-names = "default";
pinctrl-0 = <&pwm0_out>;

51
arch/arm/boot/dts/rk3188.dtsi
View File

@@ -7,6 +7,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/pinctrl/rockchip.h>
#include <dt-bindings/clock/rk3188-cru.h>
#include <dt-bindings/power/rk3188-power.h>
#include "rk3xxx.dtsi"
/ {
@@ -80,6 +81,7 @@ vop0: vop@1010c000 {
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_LCDC0>, <&cru DCLK_LCDC0>, <&cru HCLK_LCDC0>;
clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
power-domains = <&power RK3188_PD_VIO>;
resets = <&cru SRST_LCDC0_AXI>, <&cru SRST_LCDC0_AHB>, <&cru SRST_LCDC0_DCLK>;
reset-names = "axi", "ahb", "dclk";
status = "disabled";
@@ -96,6 +98,7 @@ vop1: vop@1010e000 {
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_LCDC1>, <&cru DCLK_LCDC1>, <&cru HCLK_LCDC1>;
clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
power-domains = <&power RK3188_PD_VIO>;
resets = <&cru SRST_LCDC1_AXI>, <&cru SRST_LCDC1_AHB>, <&cru SRST_LCDC1_DCLK>;
reset-names = "axi", "ahb", "dclk";
status = "disabled";
@@ -620,6 +623,7 @@ &gpu {
"ppmmu2",
"pp3",
"ppmmu3";
power-domains = <&power RK3188_PD_GPU>;
};
&i2c0 {
@@ -652,6 +656,53 @@ &i2c4 {
pinctrl-0 = <&i2c4_xfer>;
};
&pmu {
power: power-controller {
compatible = "rockchip,rk3188-power-controller";
#power-domain-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
pd_vio@RK3188_PD_VIO {
reg = <RK3188_PD_VIO>;
clocks = <&cru ACLK_LCDC0>,
<&cru ACLK_LCDC1>,
<&cru DCLK_LCDC0>,
<&cru DCLK_LCDC1>,
<&cru HCLK_LCDC0>,
<&cru HCLK_LCDC1>,
<&cru SCLK_CIF0>,
<&cru ACLK_CIF0>,
<&cru HCLK_CIF0>,
<&cru ACLK_IPP>,
<&cru HCLK_IPP>,
<&cru ACLK_RGA>,
<&cru HCLK_RGA>;
pm_qos = <&qos_lcdc0>,
<&qos_lcdc1>,
<&qos_cif0>,
<&qos_cif1>,
<&qos_ipp>,
<&qos_rga>;
};
pd_video@RK3188_PD_VIDEO {
reg = <RK3188_PD_VIDEO>;
clocks = <&cru ACLK_VDPU>,
<&cru ACLK_VEPU>,
<&cru HCLK_VDPU>,
<&cru HCLK_VEPU>;
pm_qos = <&qos_vpu>;
};
pd_gpu@RK3188_PD_GPU {
reg = <RK3188_PD_GPU>;
clocks = <&cru ACLK_GPU>;
pm_qos = <&qos_gpu>;
};
};
};
&pwm0 {
pinctrl-names = "default";
pinctrl-0 = <&pwm0_out>;

10
arch/arm/boot/dts/rk322x.dtsi
View File

@@ -493,12 +493,18 @@ cooling-maps {
map0 {
trip = <&cpu_alert0>;
cooling-device =
<&cpu0 THERMAL_NO_LIMIT 6>;
<&cpu0 THERMAL_NO_LIMIT 6>,
<&cpu1 THERMAL_NO_LIMIT 6>,
<&cpu2 THERMAL_NO_LIMIT 6>,
<&cpu3 THERMAL_NO_LIMIT 6>;
};
map1 {
trip = <&cpu_alert1>;
cooling-device =
<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};

2
arch/arm/boot/dts/rk3288-rock2-som.dtsi
View File

@@ -25,7 +25,7 @@ ext_gmac: external-gmac-clock {
vcc_flash: flash-regulator {
compatible = "regulator-fixed";
regulator-name = "vcc_sys";
regulator-name = "vcc_flash";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
startup-delay-us = <150>;

24
arch/arm/boot/dts/rk3288-veyron-mickey.dts
View File

@@ -81,8 +81,10 @@ cooling-maps {
*/
cpu_warm_limit_cpu {
trip = <&cpu_alert_warm>;
cooling-device =
<&cpu0 THERMAL_NO_LIMIT 4>;
cooling-device = <&cpu0 THERMAL_NO_LIMIT 4>,
<&cpu1 THERMAL_NO_LIMIT 4>,
<&cpu2 THERMAL_NO_LIMIT 4>,
<&cpu3 THERMAL_NO_LIMIT 4>;
};
/*
@@ -103,23 +105,25 @@ cpu_warm_limit_cpu {
*/
cpu_almost_hot_limit_cpu {
trip = <&cpu_alert_almost_hot>;
cooling-device =
<&cpu0 5 6>;
cooling-device = <&cpu0 5 6>, <&cpu1 5 6>, <&cpu2 5 6>,
<&cpu3 5 6>;
};
cpu_hot_limit_cpu {
trip = <&cpu_alert_hot>;
cooling-device =
<&cpu0 7 7>;
cooling-device = <&cpu0 7 7>, <&cpu1 7 7>, <&cpu2 7 7>,
<&cpu3 7 7>;
};
cpu_hotter_limit_cpu {
trip = <&cpu_alert_hotter>;
cooling-device =
<&cpu0 7 8>;
cooling-device = <&cpu0 7 8>, <&cpu1 7 8>, <&cpu2 7 8>,
<&cpu3 7 8>;
};
cpu_very_hot_limit_cpu {
trip = <&cpu_alert_very_hot>;
cooling-device =
<&cpu0 8 THERMAL_NO_LIMIT>;
cooling-device = <&cpu0 8 THERMAL_NO_LIMIT>,
<&cpu1 8 THERMAL_NO_LIMIT>,
<&cpu2 8 THERMAL_NO_LIMIT>,
<&cpu3 8 THERMAL_NO_LIMIT>;
};
};
};

15
arch/arm/boot/dts/rk3288.dtsi
View File

@@ -508,12 +508,18 @@ cooling-maps {
map0 {
trip = <&cpu_alert0>;
cooling-device =
<&cpu0 THERMAL_NO_LIMIT 6>;
<&cpu0 THERMAL_NO_LIMIT 6>,
<&cpu1 THERMAL_NO_LIMIT 6>,
<&cpu2 THERMAL_NO_LIMIT 6>,
<&cpu3 THERMAL_NO_LIMIT 6>;
};
map1 {
trip = <&cpu_alert1>;
cooling-device =
<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};
@@ -541,7 +547,10 @@ cooling-maps {
map0 {
trip = <&gpu_alert0>;
cooling-device =
<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
<&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
<&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
};
};
};

40
arch/arm/boot/dts/rk3xxx.dtsi
View File

@@ -147,6 +147,46 @@ uart1: serial@10126000 {
status = "disabled";
};
qos_gpu: qos@1012d000 {
compatible = "syscon";
reg = <0x1012d000 0x20>;
};
qos_vpu: qos@1012e000 {
compatible = "syscon";
reg = <0x1012e000 0x20>;
};
qos_lcdc0: qos@1012f000 {
compatible = "syscon";
reg = <0x1012f000 0x20>;
};
qos_cif0: qos@1012f080 {
compatible = "syscon";
reg = <0x1012f080 0x20>;
};
qos_ipp: qos@1012f100 {
compatible = "syscon";
reg = <0x1012f100 0x20>;
};
qos_lcdc1: qos@1012f180 {
compatible = "syscon";
reg = <0x1012f180 0x20>;
};
qos_cif1: qos@1012f200 {
compatible = "syscon";
reg = <0x1012f200 0x20>;
};
qos_rga: qos@1012f280 {
compatible = "syscon";
reg = <0x1012f280 0x20>;
};
usb_otg: usb@10180000 {
compatible = "rockchip,rk3066-usb", "snps,dwc2";
reg = <0x10180000 0x40000>;

22
include/dt-bindings/power/rk3066-power.h Normal file
View File

@@ -0,0 +1,22 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __DT_BINDINGS_POWER_RK3066_POWER_H__
#define __DT_BINDINGS_POWER_RK3066_POWER_H__
/* VD_CORE */
#define RK3066_PD_A9_0 0
#define RK3066_PD_A9_1 1
#define RK3066_PD_DBG 4
#define RK3066_PD_SCU 5
/* VD_LOGIC */
#define RK3066_PD_VIDEO 6
#define RK3066_PD_VIO 7
#define RK3066_PD_GPU 8
#define RK3066_PD_PERI 9
#define RK3066_PD_CPU 10
#define RK3066_PD_ALIVE 11
/* VD_PMU */
#define RK3066_PD_RTC 12
#endif

24
include/dt-bindings/power/rk3188-power.h Normal file
View File

@@ -0,0 +1,24 @@
/* SPDX-License-Identifier: GPL-2.0 */
#ifndef __DT_BINDINGS_POWER_RK3188_POWER_H__
#define __DT_BINDINGS_POWER_RK3188_POWER_H__
/* VD_CORE */
#define RK3188_PD_A9_0 0
#define RK3188_PD_A9_1 1
#define RK3188_PD_A9_2 2
#define RK3188_PD_A9_3 3
#define RK3188_PD_DBG 4
#define RK3188_PD_SCU 5
/* VD_LOGIC */
#define RK3188_PD_VIDEO 6
#define RK3188_PD_VIO 7
#define RK3188_PD_GPU 8
#define RK3188_PD_PERI 9
#define RK3188_PD_CPU 10
#define RK3188_PD_ALIVE 11
/* VD_PMU */
#define RK3188_PD_RTC 12
#endif