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ASoC: Intel: Remove unused code
After removal of Skylake driver there is no users left for sst-dsp and sst-ipc interfaces. Remove them. Reviewed-by: Cezary Rojewski <cezary.rojewski@intel.com> Signed-off-by: Amadeusz Sławiński <amadeuszx.slawinski@linux.intel.com> Link: https://patch.msgid.link/20241009083419.319038-1-amadeuszx.slawinski@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Amadeusz Sławiński
committed by
Mark Brown
Mark Brown
parent
f8199bbca5
commit
970d299b0a
@@ -15,9 +15,6 @@ config SND_SOC_INTEL_SST_TOPLEVEL
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if SND_SOC_INTEL_SST_TOPLEVEL
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config SND_SOC_INTEL_SST
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tristate
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config SND_SOC_INTEL_CATPT
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tristate "Haswell and Broadwell"
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depends on ACPI || COMPILE_TEST
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@@ -1,6 +1,4 @@
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# SPDX-License-Identifier: GPL-2.0-only
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snd-soc-sst-dsp-y := sst-dsp.o
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snd-soc-sst-ipc-y := sst-ipc.o
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snd-soc-acpi-intel-match-y := soc-acpi-intel-byt-match.o soc-acpi-intel-cht-match.o \
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soc-acpi-intel-hsw-bdw-match.o \
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soc-acpi-intel-skl-match.o soc-acpi-intel-kbl-match.o \
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@@ -18,5 +16,4 @@ snd-soc-acpi-intel-match-y := soc-acpi-intel-byt-match.o soc-acpi-intel-cht-matc
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snd-soc-acpi-intel-match-y += soc-acpi-intel-ssp-common.o
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obj-$(CONFIG_SND_SOC_INTEL_SST) += snd-soc-sst-dsp.o snd-soc-sst-ipc.o
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obj-$(CONFIG_SND_SOC_ACPI_INTEL_MATCH) += snd-soc-acpi-intel-match.o
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@@ -1,101 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Intel Smart Sound Technology
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*
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* Copyright (C) 2013, Intel Corporation
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*/
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#ifndef __SOUND_SOC_SST_DSP_PRIV_H
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#define __SOUND_SOC_SST_DSP_PRIV_H
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/firmware.h>
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#include "../skylake/skl-sst-dsp.h"
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/*
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* DSP Operations exported by platform Audio DSP driver.
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*/
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struct sst_ops {
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/* Shim IO */
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void (*write)(void __iomem *addr, u32 offset, u32 value);
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u32 (*read)(void __iomem *addr, u32 offset);
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/* IRQ handlers */
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irqreturn_t (*irq_handler)(int irq, void *context);
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/* SST init and free */
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int (*init)(struct sst_dsp *sst);
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void (*free)(struct sst_dsp *sst);
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};
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/*
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* Audio DSP memory offsets and addresses.
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*/
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struct sst_addr {
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u32 sram0_base;
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u32 sram1_base;
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u32 w0_stat_sz;
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u32 w0_up_sz;
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void __iomem *lpe;
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void __iomem *shim;
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};
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/*
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* Audio DSP Mailbox configuration.
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*/
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struct sst_mailbox {
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void __iomem *in_base;
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void __iomem *out_base;
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size_t in_size;
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size_t out_size;
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};
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/*
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* Generic SST Shim Interface.
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*/
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struct sst_dsp {
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/* Shared for all platforms */
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/* runtime */
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struct sst_dsp_device *sst_dev;
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spinlock_t spinlock; /* IPC locking */
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struct mutex mutex; /* DSP FW lock */
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struct device *dev;
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void *thread_context;
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int irq;
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u32 id;
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/* operations */
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struct sst_ops *ops;
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/* debug FS */
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struct dentry *debugfs_root;
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/* base addresses */
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struct sst_addr addr;
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/* mailbox */
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struct sst_mailbox mailbox;
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/* SST FW files loaded and their modules */
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struct list_head module_list;
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/* SKL data */
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const char *fw_name;
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/* To allocate CL dma buffers */
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struct skl_dsp_loader_ops dsp_ops;
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struct skl_dsp_fw_ops fw_ops;
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int sst_state;
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struct skl_cl_dev cl_dev;
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u32 intr_status;
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const struct firmware *fw;
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struct snd_dma_buffer dmab;
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};
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#endif
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@@ -1,250 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Intel Smart Sound Technology (SST) DSP Core Driver
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*
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* Copyright (C) 2013, Intel Corporation
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*/
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#include <linux/slab.h>
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#include <linux/export.h>
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/io-64-nonatomic-lo-hi.h>
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#include <linux/delay.h>
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#include "sst-dsp.h"
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#include "sst-dsp-priv.h"
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#define CREATE_TRACE_POINTS
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#include <trace/events/intel-sst.h>
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/* Internal generic low-level SST IO functions - can be overidden */
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void sst_shim32_write(void __iomem *addr, u32 offset, u32 value)
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{
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writel(value, addr + offset);
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}
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EXPORT_SYMBOL_GPL(sst_shim32_write);
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u32 sst_shim32_read(void __iomem *addr, u32 offset)
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{
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return readl(addr + offset);
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}
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EXPORT_SYMBOL_GPL(sst_shim32_read);
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void sst_shim32_write64(void __iomem *addr, u32 offset, u64 value)
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{
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writeq(value, addr + offset);
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}
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EXPORT_SYMBOL_GPL(sst_shim32_write64);
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u64 sst_shim32_read64(void __iomem *addr, u32 offset)
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{
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return readq(addr + offset);
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}
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EXPORT_SYMBOL_GPL(sst_shim32_read64);
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/* Public API */
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void sst_dsp_shim_write(struct sst_dsp *sst, u32 offset, u32 value)
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{
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unsigned long flags;
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spin_lock_irqsave(&sst->spinlock, flags);
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sst->ops->write(sst->addr.shim, offset, value);
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spin_unlock_irqrestore(&sst->spinlock, flags);
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}
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EXPORT_SYMBOL_GPL(sst_dsp_shim_write);
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u32 sst_dsp_shim_read(struct sst_dsp *sst, u32 offset)
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{
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unsigned long flags;
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u32 val;
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spin_lock_irqsave(&sst->spinlock, flags);
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val = sst->ops->read(sst->addr.shim, offset);
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spin_unlock_irqrestore(&sst->spinlock, flags);
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return val;
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}
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EXPORT_SYMBOL_GPL(sst_dsp_shim_read);
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void sst_dsp_shim_write_unlocked(struct sst_dsp *sst, u32 offset, u32 value)
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{
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sst->ops->write(sst->addr.shim, offset, value);
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}
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EXPORT_SYMBOL_GPL(sst_dsp_shim_write_unlocked);
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u32 sst_dsp_shim_read_unlocked(struct sst_dsp *sst, u32 offset)
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{
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return sst->ops->read(sst->addr.shim, offset);
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}
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EXPORT_SYMBOL_GPL(sst_dsp_shim_read_unlocked);
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int sst_dsp_shim_update_bits_unlocked(struct sst_dsp *sst, u32 offset,
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u32 mask, u32 value)
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{
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bool change;
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unsigned int old, new;
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u32 ret;
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ret = sst_dsp_shim_read_unlocked(sst, offset);
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old = ret;
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new = (old & (~mask)) | (value & mask);
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change = (old != new);
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if (change)
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sst_dsp_shim_write_unlocked(sst, offset, new);
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return change;
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}
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EXPORT_SYMBOL_GPL(sst_dsp_shim_update_bits_unlocked);
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/* This is for registers bits with attribute RWC */
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void sst_dsp_shim_update_bits_forced_unlocked(struct sst_dsp *sst, u32 offset,
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u32 mask, u32 value)
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{
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unsigned int old, new;
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u32 ret;
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ret = sst_dsp_shim_read_unlocked(sst, offset);
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old = ret;
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new = (old & (~mask)) | (value & mask);
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sst_dsp_shim_write_unlocked(sst, offset, new);
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}
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EXPORT_SYMBOL_GPL(sst_dsp_shim_update_bits_forced_unlocked);
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int sst_dsp_shim_update_bits(struct sst_dsp *sst, u32 offset,
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u32 mask, u32 value)
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{
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unsigned long flags;
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bool change;
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spin_lock_irqsave(&sst->spinlock, flags);
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change = sst_dsp_shim_update_bits_unlocked(sst, offset, mask, value);
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spin_unlock_irqrestore(&sst->spinlock, flags);
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return change;
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}
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EXPORT_SYMBOL_GPL(sst_dsp_shim_update_bits);
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/* This is for registers bits with attribute RWC */
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void sst_dsp_shim_update_bits_forced(struct sst_dsp *sst, u32 offset,
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u32 mask, u32 value)
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{
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unsigned long flags;
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spin_lock_irqsave(&sst->spinlock, flags);
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sst_dsp_shim_update_bits_forced_unlocked(sst, offset, mask, value);
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spin_unlock_irqrestore(&sst->spinlock, flags);
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}
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EXPORT_SYMBOL_GPL(sst_dsp_shim_update_bits_forced);
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int sst_dsp_register_poll(struct sst_dsp *ctx, u32 offset, u32 mask,
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u32 target, u32 time, char *operation)
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{
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u32 reg;
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unsigned long timeout;
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int k = 0, s = 500;
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/*
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* split the loop into sleeps of varying resolution. more accurately,
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* the range of wakeups are:
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* Phase 1(first 5ms): min sleep 0.5ms; max sleep 1ms.
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* Phase 2:( 5ms to 10ms) : min sleep 0.5ms; max sleep 10ms
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* (usleep_range (500, 1000) and usleep_range(5000, 10000) are
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* both possible in this phase depending on whether k > 10 or not).
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* Phase 3: (beyond 10 ms) min sleep 5ms; max sleep 10ms.
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*/
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timeout = jiffies + msecs_to_jiffies(time);
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while ((((reg = sst_dsp_shim_read_unlocked(ctx, offset)) & mask) != target)
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&& time_before(jiffies, timeout)) {
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k++;
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if (k > 10)
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s = 5000;
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usleep_range(s, 2*s);
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}
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if ((reg & mask) == target) {
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dev_dbg(ctx->dev, "FW Poll Status: reg=%#x %s successful\n",
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reg, operation);
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return 0;
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}
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dev_dbg(ctx->dev, "FW Poll Status: reg=%#x %s timedout\n",
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reg, operation);
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return -ETIME;
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}
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EXPORT_SYMBOL_GPL(sst_dsp_register_poll);
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int sst_dsp_mailbox_init(struct sst_dsp *sst, u32 inbox_offset, size_t inbox_size,
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u32 outbox_offset, size_t outbox_size)
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{
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sst->mailbox.in_base = sst->addr.lpe + inbox_offset;
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sst->mailbox.out_base = sst->addr.lpe + outbox_offset;
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sst->mailbox.in_size = inbox_size;
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sst->mailbox.out_size = outbox_size;
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return 0;
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}
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EXPORT_SYMBOL_GPL(sst_dsp_mailbox_init);
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void sst_dsp_outbox_write(struct sst_dsp *sst, void *message, size_t bytes)
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{
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u32 i;
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trace_sst_ipc_outbox_write(bytes);
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memcpy_toio(sst->mailbox.out_base, message, bytes);
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for (i = 0; i < bytes; i += 4)
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trace_sst_ipc_outbox_wdata(i, *(u32 *)(message + i));
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}
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EXPORT_SYMBOL_GPL(sst_dsp_outbox_write);
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void sst_dsp_outbox_read(struct sst_dsp *sst, void *message, size_t bytes)
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{
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u32 i;
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trace_sst_ipc_outbox_read(bytes);
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memcpy_fromio(message, sst->mailbox.out_base, bytes);
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for (i = 0; i < bytes; i += 4)
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trace_sst_ipc_outbox_rdata(i, *(u32 *)(message + i));
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}
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EXPORT_SYMBOL_GPL(sst_dsp_outbox_read);
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void sst_dsp_inbox_write(struct sst_dsp *sst, void *message, size_t bytes)
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{
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u32 i;
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trace_sst_ipc_inbox_write(bytes);
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memcpy_toio(sst->mailbox.in_base, message, bytes);
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for (i = 0; i < bytes; i += 4)
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trace_sst_ipc_inbox_wdata(i, *(u32 *)(message + i));
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}
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EXPORT_SYMBOL_GPL(sst_dsp_inbox_write);
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void sst_dsp_inbox_read(struct sst_dsp *sst, void *message, size_t bytes)
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{
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u32 i;
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trace_sst_ipc_inbox_read(bytes);
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memcpy_fromio(message, sst->mailbox.in_base, bytes);
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for (i = 0; i < bytes; i += 4)
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trace_sst_ipc_inbox_rdata(i, *(u32 *)(message + i));
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}
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EXPORT_SYMBOL_GPL(sst_dsp_inbox_read);
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/* Module information */
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MODULE_AUTHOR("Liam Girdwood");
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MODULE_DESCRIPTION("Intel SST Core");
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MODULE_LICENSE("GPL v2");
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@@ -1,61 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Intel Smart Sound Technology (SST) Core
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*
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* Copyright (C) 2013, Intel Corporation
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*/
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#ifndef __SOUND_SOC_SST_DSP_H
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#define __SOUND_SOC_SST_DSP_H
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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struct sst_dsp;
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/*
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* SST Device.
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*
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* This structure is populated by the SST core driver.
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*/
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struct sst_dsp_device {
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/* Mandatory fields */
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struct sst_ops *ops;
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irqreturn_t (*thread)(int irq, void *context);
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void *thread_context;
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};
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/* SHIM Read / Write */
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void sst_dsp_shim_write(struct sst_dsp *sst, u32 offset, u32 value);
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u32 sst_dsp_shim_read(struct sst_dsp *sst, u32 offset);
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int sst_dsp_shim_update_bits(struct sst_dsp *sst, u32 offset,
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u32 mask, u32 value);
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void sst_dsp_shim_update_bits_forced(struct sst_dsp *sst, u32 offset,
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u32 mask, u32 value);
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/* SHIM Read / Write Unlocked for callers already holding sst lock */
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void sst_dsp_shim_write_unlocked(struct sst_dsp *sst, u32 offset, u32 value);
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u32 sst_dsp_shim_read_unlocked(struct sst_dsp *sst, u32 offset);
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int sst_dsp_shim_update_bits_unlocked(struct sst_dsp *sst, u32 offset,
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u32 mask, u32 value);
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void sst_dsp_shim_update_bits_forced_unlocked(struct sst_dsp *sst, u32 offset,
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u32 mask, u32 value);
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/* Internal generic low-level SST IO functions - can be overidden */
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void sst_shim32_write(void __iomem *addr, u32 offset, u32 value);
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u32 sst_shim32_read(void __iomem *addr, u32 offset);
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void sst_shim32_write64(void __iomem *addr, u32 offset, u64 value);
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u64 sst_shim32_read64(void __iomem *addr, u32 offset);
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/* Mailbox management */
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int sst_dsp_mailbox_init(struct sst_dsp *sst, u32 inbox_offset,
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size_t inbox_size, u32 outbox_offset, size_t outbox_size);
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void sst_dsp_inbox_write(struct sst_dsp *sst, void *message, size_t bytes);
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void sst_dsp_inbox_read(struct sst_dsp *sst, void *message, size_t bytes);
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void sst_dsp_outbox_write(struct sst_dsp *sst, void *message, size_t bytes);
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void sst_dsp_outbox_read(struct sst_dsp *sst, void *message, size_t bytes);
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int sst_dsp_register_poll(struct sst_dsp *ctx, u32 offset, u32 mask,
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u32 target, u32 time, char *operation);
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#endif
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||||
@@ -1,294 +0,0 @@
|
||||
// SPDX-License-Identifier: GPL-2.0-only
|
||||
/*
|
||||
* Intel SST generic IPC Support
|
||||
*
|
||||
* Copyright (C) 2015, Intel Corporation
|
||||
*/
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/list.h>
|
||||
#include <linux/wait.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/device.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/workqueue.h>
|
||||
#include <linux/sched.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <sound/asound.h>
|
||||
|
||||
#include "sst-dsp.h"
|
||||
#include "sst-dsp-priv.h"
|
||||
#include "sst-ipc.h"
|
||||
|
||||
/* IPC message timeout (msecs) */
|
||||
#define IPC_TIMEOUT_MSECS 300
|
||||
|
||||
#define IPC_EMPTY_LIST_SIZE 8
|
||||
|
||||
/* locks held by caller */
|
||||
static struct ipc_message *msg_get_empty(struct sst_generic_ipc *ipc)
|
||||
{
|
||||
struct ipc_message *msg = NULL;
|
||||
|
||||
if (!list_empty(&ipc->empty_list)) {
|
||||
msg = list_first_entry(&ipc->empty_list, struct ipc_message,
|
||||
list);
|
||||
list_del(&msg->list);
|
||||
}
|
||||
|
||||
return msg;
|
||||
}
|
||||
|
||||
static int tx_wait_done(struct sst_generic_ipc *ipc,
|
||||
struct ipc_message *msg, struct sst_ipc_message *reply)
|
||||
{
|
||||
unsigned long flags;
|
||||
int ret;
|
||||
|
||||
/* wait for DSP completion (in all cases atm inc pending) */
|
||||
ret = wait_event_timeout(msg->waitq, msg->complete,
|
||||
msecs_to_jiffies(IPC_TIMEOUT_MSECS));
|
||||
|
||||
spin_lock_irqsave(&ipc->dsp->spinlock, flags);
|
||||
if (ret == 0) {
|
||||
if (ipc->ops.shim_dbg != NULL)
|
||||
ipc->ops.shim_dbg(ipc, "message timeout");
|
||||
|
||||
list_del(&msg->list);
|
||||
ret = -ETIMEDOUT;
|
||||
} else {
|
||||
|
||||
/* copy the data returned from DSP */
|
||||
if (reply) {
|
||||
reply->header = msg->rx.header;
|
||||
if (reply->data)
|
||||
memcpy(reply->data, msg->rx.data, msg->rx.size);
|
||||
}
|
||||
ret = msg->errno;
|
||||
}
|
||||
|
||||
list_add_tail(&msg->list, &ipc->empty_list);
|
||||
spin_unlock_irqrestore(&ipc->dsp->spinlock, flags);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int ipc_tx_message(struct sst_generic_ipc *ipc,
|
||||
struct sst_ipc_message request,
|
||||
struct sst_ipc_message *reply, int wait)
|
||||
{
|
||||
struct ipc_message *msg;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&ipc->dsp->spinlock, flags);
|
||||
|
||||
msg = msg_get_empty(ipc);
|
||||
if (msg == NULL) {
|
||||
spin_unlock_irqrestore(&ipc->dsp->spinlock, flags);
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
msg->tx.header = request.header;
|
||||
msg->tx.size = request.size;
|
||||
msg->rx.header = 0;
|
||||
msg->rx.size = reply ? reply->size : 0;
|
||||
msg->wait = wait;
|
||||
msg->errno = 0;
|
||||
msg->pending = false;
|
||||
msg->complete = false;
|
||||
|
||||
if ((request.size) && (ipc->ops.tx_data_copy != NULL))
|
||||
ipc->ops.tx_data_copy(msg, request.data, request.size);
|
||||
|
||||
list_add_tail(&msg->list, &ipc->tx_list);
|
||||
schedule_work(&ipc->kwork);
|
||||
spin_unlock_irqrestore(&ipc->dsp->spinlock, flags);
|
||||
|
||||
if (wait)
|
||||
return tx_wait_done(ipc, msg, reply);
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int msg_empty_list_init(struct sst_generic_ipc *ipc)
|
||||
{
|
||||
int i;
|
||||
|
||||
ipc->msg = kcalloc(IPC_EMPTY_LIST_SIZE, sizeof(struct ipc_message),
|
||||
GFP_KERNEL);
|
||||
if (ipc->msg == NULL)
|
||||
return -ENOMEM;
|
||||
|
||||
for (i = 0; i < IPC_EMPTY_LIST_SIZE; i++) {
|
||||
ipc->msg[i].tx.data = kzalloc(ipc->tx_data_max_size, GFP_KERNEL);
|
||||
if (ipc->msg[i].tx.data == NULL)
|
||||
goto free_mem;
|
||||
|
||||
ipc->msg[i].rx.data = kzalloc(ipc->rx_data_max_size, GFP_KERNEL);
|
||||
if (ipc->msg[i].rx.data == NULL) {
|
||||
kfree(ipc->msg[i].tx.data);
|
||||
goto free_mem;
|
||||
}
|
||||
|
||||
init_waitqueue_head(&ipc->msg[i].waitq);
|
||||
list_add(&ipc->msg[i].list, &ipc->empty_list);
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
free_mem:
|
||||
while (i > 0) {
|
||||
kfree(ipc->msg[i-1].tx.data);
|
||||
kfree(ipc->msg[i-1].rx.data);
|
||||
--i;
|
||||
}
|
||||
kfree(ipc->msg);
|
||||
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
static void ipc_tx_msgs(struct work_struct *work)
|
||||
{
|
||||
struct sst_generic_ipc *ipc =
|
||||
container_of(work, struct sst_generic_ipc, kwork);
|
||||
struct ipc_message *msg;
|
||||
|
||||
spin_lock_irq(&ipc->dsp->spinlock);
|
||||
|
||||
while (!list_empty(&ipc->tx_list) && !ipc->pending) {
|
||||
/* if the DSP is busy, we will TX messages after IRQ.
|
||||
* also postpone if we are in the middle of processing
|
||||
* completion irq
|
||||
*/
|
||||
if (ipc->ops.is_dsp_busy && ipc->ops.is_dsp_busy(ipc->dsp)) {
|
||||
dev_dbg(ipc->dev, "ipc_tx_msgs dsp busy\n");
|
||||
break;
|
||||
}
|
||||
|
||||
msg = list_first_entry(&ipc->tx_list, struct ipc_message, list);
|
||||
list_move(&msg->list, &ipc->rx_list);
|
||||
|
||||
if (ipc->ops.tx_msg != NULL)
|
||||
ipc->ops.tx_msg(ipc, msg);
|
||||
}
|
||||
|
||||
spin_unlock_irq(&ipc->dsp->spinlock);
|
||||
}
|
||||
|
||||
int sst_ipc_tx_message_wait(struct sst_generic_ipc *ipc,
|
||||
struct sst_ipc_message request, struct sst_ipc_message *reply)
|
||||
{
|
||||
int ret;
|
||||
|
||||
/*
|
||||
* DSP maybe in lower power active state, so
|
||||
* check if the DSP supports DSP lp On method
|
||||
* if so invoke that before sending IPC
|
||||
*/
|
||||
if (ipc->ops.check_dsp_lp_on)
|
||||
if (ipc->ops.check_dsp_lp_on(ipc->dsp, true))
|
||||
return -EIO;
|
||||
|
||||
ret = ipc_tx_message(ipc, request, reply, 1);
|
||||
|
||||
if (ipc->ops.check_dsp_lp_on)
|
||||
if (ipc->ops.check_dsp_lp_on(ipc->dsp, false))
|
||||
return -EIO;
|
||||
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(sst_ipc_tx_message_wait);
|
||||
|
||||
int sst_ipc_tx_message_nowait(struct sst_generic_ipc *ipc,
|
||||
struct sst_ipc_message request)
|
||||
{
|
||||
return ipc_tx_message(ipc, request, NULL, 0);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(sst_ipc_tx_message_nowait);
|
||||
|
||||
int sst_ipc_tx_message_nopm(struct sst_generic_ipc *ipc,
|
||||
struct sst_ipc_message request, struct sst_ipc_message *reply)
|
||||
{
|
||||
return ipc_tx_message(ipc, request, reply, 1);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(sst_ipc_tx_message_nopm);
|
||||
|
||||
struct ipc_message *sst_ipc_reply_find_msg(struct sst_generic_ipc *ipc,
|
||||
u64 header)
|
||||
{
|
||||
struct ipc_message *msg;
|
||||
u64 mask;
|
||||
|
||||
if (ipc->ops.reply_msg_match != NULL)
|
||||
header = ipc->ops.reply_msg_match(header, &mask);
|
||||
else
|
||||
mask = (u64)-1;
|
||||
|
||||
if (list_empty(&ipc->rx_list)) {
|
||||
dev_err(ipc->dev, "error: rx list empty but received 0x%llx\n",
|
||||
header);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
list_for_each_entry(msg, &ipc->rx_list, list) {
|
||||
if ((msg->tx.header & mask) == header)
|
||||
return msg;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(sst_ipc_reply_find_msg);
|
||||
|
||||
/* locks held by caller */
|
||||
void sst_ipc_tx_msg_reply_complete(struct sst_generic_ipc *ipc,
|
||||
struct ipc_message *msg)
|
||||
{
|
||||
msg->complete = true;
|
||||
|
||||
if (!msg->wait)
|
||||
list_add_tail(&msg->list, &ipc->empty_list);
|
||||
else
|
||||
wake_up(&msg->waitq);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(sst_ipc_tx_msg_reply_complete);
|
||||
|
||||
int sst_ipc_init(struct sst_generic_ipc *ipc)
|
||||
{
|
||||
int ret;
|
||||
|
||||
INIT_LIST_HEAD(&ipc->tx_list);
|
||||
INIT_LIST_HEAD(&ipc->rx_list);
|
||||
INIT_LIST_HEAD(&ipc->empty_list);
|
||||
init_waitqueue_head(&ipc->wait_txq);
|
||||
|
||||
ret = msg_empty_list_init(ipc);
|
||||
if (ret < 0)
|
||||
return -ENOMEM;
|
||||
|
||||
INIT_WORK(&ipc->kwork, ipc_tx_msgs);
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(sst_ipc_init);
|
||||
|
||||
void sst_ipc_fini(struct sst_generic_ipc *ipc)
|
||||
{
|
||||
int i;
|
||||
|
||||
cancel_work_sync(&ipc->kwork);
|
||||
|
||||
if (ipc->msg) {
|
||||
for (i = 0; i < IPC_EMPTY_LIST_SIZE; i++) {
|
||||
kfree(ipc->msg[i].tx.data);
|
||||
kfree(ipc->msg[i].rx.data);
|
||||
}
|
||||
kfree(ipc->msg);
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(sst_ipc_fini);
|
||||
|
||||
/* Module information */
|
||||
MODULE_AUTHOR("Jin Yao");
|
||||
MODULE_DESCRIPTION("Intel SST IPC generic");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
@@ -1,86 +0,0 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
/*
|
||||
* Intel SST generic IPC Support
|
||||
*
|
||||
* Copyright (C) 2015, Intel Corporation
|
||||
*/
|
||||
|
||||
#ifndef __SST_GENERIC_IPC_H
|
||||
#define __SST_GENERIC_IPC_H
|
||||
|
||||
#include <linux/types.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/wait.h>
|
||||
#include <linux/list.h>
|
||||
#include <linux/workqueue.h>
|
||||
#include <linux/sched.h>
|
||||
|
||||
struct sst_ipc_message {
|
||||
u64 header;
|
||||
void *data;
|
||||
size_t size;
|
||||
};
|
||||
|
||||
struct ipc_message {
|
||||
struct list_head list;
|
||||
struct sst_ipc_message tx;
|
||||
struct sst_ipc_message rx;
|
||||
|
||||
wait_queue_head_t waitq;
|
||||
bool pending;
|
||||
bool complete;
|
||||
bool wait;
|
||||
int errno;
|
||||
};
|
||||
|
||||
struct sst_generic_ipc;
|
||||
struct sst_dsp;
|
||||
|
||||
struct sst_plat_ipc_ops {
|
||||
void (*tx_msg)(struct sst_generic_ipc *, struct ipc_message *);
|
||||
void (*shim_dbg)(struct sst_generic_ipc *, const char *);
|
||||
void (*tx_data_copy)(struct ipc_message *, char *, size_t);
|
||||
u64 (*reply_msg_match)(u64 header, u64 *mask);
|
||||
bool (*is_dsp_busy)(struct sst_dsp *dsp);
|
||||
int (*check_dsp_lp_on)(struct sst_dsp *dsp, bool state);
|
||||
};
|
||||
|
||||
/* SST generic IPC data */
|
||||
struct sst_generic_ipc {
|
||||
struct device *dev;
|
||||
struct sst_dsp *dsp;
|
||||
|
||||
/* IPC messaging */
|
||||
struct list_head tx_list;
|
||||
struct list_head rx_list;
|
||||
struct list_head empty_list;
|
||||
wait_queue_head_t wait_txq;
|
||||
struct task_struct *tx_thread;
|
||||
struct work_struct kwork;
|
||||
bool pending;
|
||||
struct ipc_message *msg;
|
||||
int tx_data_max_size;
|
||||
int rx_data_max_size;
|
||||
|
||||
struct sst_plat_ipc_ops ops;
|
||||
};
|
||||
|
||||
int sst_ipc_tx_message_wait(struct sst_generic_ipc *ipc,
|
||||
struct sst_ipc_message request, struct sst_ipc_message *reply);
|
||||
|
||||
int sst_ipc_tx_message_nowait(struct sst_generic_ipc *ipc,
|
||||
struct sst_ipc_message request);
|
||||
|
||||
int sst_ipc_tx_message_nopm(struct sst_generic_ipc *ipc,
|
||||
struct sst_ipc_message request, struct sst_ipc_message *reply);
|
||||
|
||||
struct ipc_message *sst_ipc_reply_find_msg(struct sst_generic_ipc *ipc,
|
||||
u64 header);
|
||||
|
||||
void sst_ipc_tx_msg_reply_complete(struct sst_generic_ipc *ipc,
|
||||
struct ipc_message *msg);
|
||||
|
||||
int sst_ipc_init(struct sst_generic_ipc *ipc);
|
||||
void sst_ipc_fini(struct sst_generic_ipc *ipc);
|
||||
|
||||
#endif
|
||||
Reference in New Issue
Block a user