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Merge tag 'stm32-dt-for-v6.17-1' of https://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into soc/dt

Browse Source 
STM32 DT for v6.17, round 1

Highlights:
----------

- MPU:
  - STM32MP13:
    -Add Ethernet MAC adress efuse support.

  - STMP32MP15:
    - Add stm32mp157f-DK2 board support. This board embedds the same
      conectivity devices, DDR ... than stm32mp157c-dk2.
      However there are two differences: STM32MP157F SoC which allows
      overdrive OPP and the SCMI support for system features like
      clocks and regulators.

  - STM32MP25:
    - Fix tick timer for low power use cases.
    - Add timer support.

* tag 'stm32-dt-for-v6.17-1' of https://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32:
  arm64: dts: st: remove empty line in stm32mp251.dtsi
  arm64: dts: st: fix timer used for ticks
  arm64: defconfig: Enable STM32 Octo Memory Manager and OcstoSPI driver
  ARM: dts: stm32: add stm32mp157f-dk2 board support
  dt-bindings: arm: stm32: add STM32MP157F-DK2 board compatible
  ARM: dts: stm32: optee async notif interrupt for MP15 scmi variants
  ARM: dts: stm32: use internal regulators bindings for MP15 scmi variants
  dt-bindings: regulator: Add STM32MP15 SCMI regulator identifiers
  ARM: dts: stm32: use 'typec' generic name for stusb1600 on stm32mp15xx-dkx
  ARM: dts: stm32: fullfill diversity with OPP for STM32M15xF SOCs
  ARM: dts: stm32: add system-clock-direction-out on stm32mp15xx-dkx
  arm64: defconfig: enable STM32 timers drivers
  arm64: dts: st: add timer nodes on stm32mp257f-ev1
  arm64: dts: st: add timer pins for stm32mp257f-ev1
  arm64: dts: st: add timer nodes on stm32mp251
  ARM: dts: stm32: Add nvmem-cells to ethernet nodes for constant mac-addresses

Link: https://lore.kernel.org/r/b3e3363b-1ea5-457c-b244-2cbe26f7d6e4@foss.st.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
2025-07-21 17:04:38 +02:00
parent 4340c8d32a 1a32f7427e
commit 96a96de2cc
14 changed files with 1098 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
Documentation/devicetree/bindings/arm/stm32/stm32.yaml
View File

@@ -121,6 +121,7 @@ properties:
- st,stm32mp157a-dk1-scmi
- st,stm32mp157c-dk2
- st,stm32mp157c-dk2-scmi
- st,stm32mp157f-dk2
- const: st,stm32mp157
- items:

3
arch/arm/boot/dts/st/Makefile
View File

@@ -72,7 +72,8 @@ dtb-$(CONFIG_ARCH_STM32) += \
stm32mp157c-odyssey.dtb \
stm32mp157c-osd32mp1-red.dtb \
stm32mp157c-phycore-stm32mp1-3.dtb \
stm32mp157c-ultra-fly-sbc.dtb
stm32mp157c-ultra-fly-sbc.dtb \
stm32mp157f-dk2.dtb
dtb-$(CONFIG_ARCH_U8500) += \
ste-snowball.dtb \
ste-hrefprev60-stuib.dtb \

2
arch/arm/boot/dts/st/stm32mp131.dtsi
View File

@@ -1614,6 +1614,8 @@ ethernet1: ethernet@5800a000 {
snps,axi-config = <&stmmac_axi_config_1>;
snps,tso;
access-controllers = <&etzpc 48>;
nvmem-cells = <&ethernet_mac1_address>;
nvmem-cell-names = "mac-address";
status = "disabled";
stmmac_axi_config_1: stmmac-axi-config {

2
arch/arm/boot/dts/st/stm32mp133.dtsi
View File

@@ -93,6 +93,8 @@ ethernet2: ethernet@5800e000 {
snps,axi-config = <&stmmac_axi_config_2>;
snps,tso;
access-controllers = <&etzpc 49>;
nvmem-cells = <&ethernet_mac2_address>;
nvmem-cell-names = "mac-address";
status = "disabled";
stmmac_axi_config_2: stmmac-axi-config {

10
arch/arm/boot/dts/st/stm32mp15-scmi.dtsi
View File

@@ -4,11 +4,15 @@
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/
#include <dt-bindings/regulator/st,stm32mp15-regulator.h>
/ {
firmware {
optee: optee {
compatible = "linaro,optee-tz";
method = "smc";
interrupt-parent = <&intc>;
interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
};
scmi: scmi {
@@ -35,21 +39,21 @@ scmi_reguls: regulators {
#size-cells = <0>;
scmi_reg11: regulator@0 {
reg = <0>;
reg = <VOLTD_SCMI_REG11>;
regulator-name = "reg11";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
};
scmi_reg18: regulator@1 {
reg = <1>;
reg = <VOLTD_SCMI_REG18>;
regulator-name = "reg18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
scmi_usb33: regulator@2 {
reg = <2>;
reg = <VOLTD_SCMI_USB33>;
regulator-name = "usb33";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;

196
arch/arm/boot/dts/st/stm32mp157f-dk2-scmi.dtsi Normal file
View File

@@ -0,0 +1,196 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2025 - All Rights Reserved
* Author: Amelie Delaunay <amelie.delaunay@foss.st.com> for STMicroelectronics.
*/
#include "stm32mp15-scmi.dtsi"
/ {
reserved-memory {
optee@de000000 {
reg = <0xde000000 0x2000000>;
no-map;
};
};
arm_wdt: watchdog {
compatible = "arm,smc-wdt";
arm,smc-id = <0xbc000000>;
status = "disabled";
};
};
&adc {
vdd-supply = <&scmi_vdd>;
vdda-supply = <&scmi_vdd>;
};
&cpu0 {
clocks = <&scmi_clk CK_SCMI_MPU>;
};
&cpu1 {
clocks = <&scmi_clk CK_SCMI_MPU>;
};
&cryp1 {
clocks = <&scmi_clk CK_SCMI_CRYP1>;
resets = <&scmi_reset RST_SCMI_CRYP1>;
};
&cs42l51 {
VL-supply = <&scmi_v3v3>;
VD-supply = <&scmi_v1v8_audio>;
VA-supply = <&scmi_v1v8_audio>;
VAHP-supply = <&scmi_v1v8_audio>;
};
&dsi {
phy-dsi-supply = <&scmi_reg18>;
clocks = <&rcc DSI>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
};
&gpioz {
clocks = <&scmi_clk CK_SCMI_GPIOZ>;
};
&hash1 {
clocks = <&scmi_clk CK_SCMI_HASH1>;
resets = <&scmi_reset RST_SCMI_HASH1>;
};
&i2c1 {
hdmi-transmitter@39 {
iovcc-supply = <&scmi_v3v3_hdmi>;
cvcc12-supply = <&scmi_v1v2_hdmi>;
};
};
&iwdg2 {
clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
status = "disabled";
};
&m4_rproc {
/delete-property/ st,syscfg-holdboot;
resets = <&scmi_reset RST_SCMI_MCU>,
<&scmi_reset RST_SCMI_MCU_HOLD_BOOT>;
reset-names = "mcu_rst", "hold_boot";
};
&mdma1 {
resets = <&scmi_reset RST_SCMI_MDMA>;
};
&optee {
interrupt-parent = <&intc>;
interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
};
&pwr_regulators {
vdd-supply = <&scmi_vdd>;
vdd_3v3_usbfs-supply = <&scmi_vdd_usb>;
status = "disabled";
};
&rcc {
compatible = "st,stm32mp1-rcc-secure", "syscon";
clock-names = "hse", "hsi", "csi", "lse", "lsi";
clocks = <&scmi_clk CK_SCMI_HSE>,
<&scmi_clk CK_SCMI_HSI>,
<&scmi_clk CK_SCMI_CSI>,
<&scmi_clk CK_SCMI_LSE>,
<&scmi_clk CK_SCMI_LSI>;
};
&rng1 {
clocks = <&scmi_clk CK_SCMI_RNG1>;
resets = <&scmi_reset RST_SCMI_RNG1>;
};
&rtc {
clocks = <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>;
};
&scmi_reguls {
scmi_vddcore: regulator@3 {
reg = <VOLTD_SCMI_STPMIC1_BUCK1>;
regulator-name = "vddcore";
};
scmi_vdd: regulator@5 {
reg = <VOLTD_SCMI_STPMIC1_BUCK3>;
regulator-name = "vdd";
};
scmi_v3v3: regulator@6 {
reg = <VOLTD_SCMI_STPMIC1_BUCK4>;
regulator-name = "v3v3";
};
scmi_v1v8_audio: regulator@7 {
reg = <VOLTD_SCMI_STPMIC1_LDO1>;
regulator-name = "v1v8_audio";
};
scmi_v3v3_hdmi: regulator@8 {
reg = <VOLTD_SCMI_STPMIC1_LDO2>;
regulator-name = "v3v3_hdmi";
};
scmi_vdd_usb: regulator@a {
reg = <VOLTD_SCMI_STPMIC1_LDO4>;
regulator-name = "vdd_usb";
};
scmi_vdda: regulator@b {
reg = <VOLTD_SCMI_STPMIC1_LDO5>;
regulator-name = "vdda";
};
scmi_v1v2_hdmi: regulator@c {
reg = <VOLTD_SCMI_STPMIC1_LDO6>;
regulator-name = "v1v2_hdmi";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
};
scmi_vbus_otg: regulator@f {
reg = <VOLTD_SCMI_STPMIC1_PWR_SW1>;
regulator-name = "vbus_otg";
};
scmi_vbus_sw: regulator@10 {
reg = <VOLTD_SCMI_STPMIC1_PWR_SW2>;
regulator-name = "vbus_sw";
};
};
&sdmmc1 {
vmmc-supply = <&scmi_v3v3>;
};
&sdmmc3 {
vmmc-supply = <&scmi_v3v3>;
};
&usbh_ehci {
hub@1 {
vdd-supply = <&scmi_v3v3>;
};
};
&usbphyc_port0 {
phy-supply = <&scmi_vdd_usb>;
};
&usbphyc_port1 {
phy-supply = <&scmi_vdd_usb>;
};
&vrefbuf {
vdda-supply = <&scmi_vdd>;
};

179
arch/arm/boot/dts/st/stm32mp157f-dk2.dts Normal file
View File

@@ -0,0 +1,179 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2025 - All Rights Reserved
* Author: Amelie Delaunay <amelie.delaunay@foss.st.com> for STMicroelectronics.
*/
/dts-v1/;
#include "stm32mp157.dtsi"
#include "stm32mp15xf.dtsi"
#include "stm32mp15-pinctrl.dtsi"
#include "stm32mp15xxac-pinctrl.dtsi"
#include "stm32mp15xx-dkx.dtsi"
#include "stm32mp157f-dk2-scmi.dtsi"
/ {
model = "STMicroelectronics STM32MP157F-DK2 Discovery Board";
compatible = "st,stm32mp157f-dk2", "st,stm32mp157";
aliases {
ethernet0 = &ethernet0;
serial3 = &usart2;
};
chosen {
stdout-path = "serial0:115200n8";
};
wifi_pwrseq: wifi-pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpioh 4 GPIO_ACTIVE_LOW>;
};
};
&arm_wdt {
timeout-sec = <32>;
status = "okay";
};
&cryp1 {
status = "okay";
};
&dsi {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
panel@0 {
compatible = "orisetech,otm8009a";
reg = <0>;
reset-gpios = <&gpioe 4 GPIO_ACTIVE_LOW>;
power-supply = <&scmi_v3v3>;
status = "okay";
port {
panel_in: endpoint {
remote-endpoint = <&dsi_out>;
};
};
};
};
&dsi_in {
remote-endpoint = <&ltdc_ep1_out>;
};
&dsi_out {
remote-endpoint = <&panel_in>;
};
&i2c1 {
touchscreen@38 {
compatible = "focaltech,ft6236";
reg = <0x38>;
interrupts = <2 IRQ_TYPE_EDGE_FALLING>;
interrupt-parent = <&gpiof>;
touchscreen-size-x = <480>;
touchscreen-size-y = <800>;
status = "okay";
};
};
/* I2C4 is managed by OP-TEE */
&i2c4 {
status = "disabled";
/* i2c4 subnodes, which won't be managed by Linux */
typec@28 {
status = "disabled";
connector {
status = "disabled";
};
};
stpmic@33 {
status = "disabled";
};
};
&ltdc {
status = "okay";
port {
#address-cells = <1>;
#size-cells = <0>;
ltdc_ep1_out: endpoint@1 {
reg = <1>;
remote-endpoint = <&dsi_in>;
};
};
};
&rtc {
pinctrl-names = "default";
pinctrl-0 = <&rtc_rsvd_pins_a>;
rtc_lsco_pins_a: rtc-lsco-0 {
pins = "out2_rmp";
function = "lsco";
};
};
/* Wifi */
&sdmmc2 {
pinctrl-names = "default", "opendrain", "sleep";
pinctrl-0 = <&sdmmc2_b4_pins_a>;
pinctrl-1 = <&sdmmc2_b4_od_pins_a>;
pinctrl-2 = <&sdmmc2_b4_sleep_pins_a>;
non-removable;
cap-sdio-irq;
st,neg-edge;
bus-width = <4>;
vmmc-supply = <&scmi_v3v3>;
mmc-pwrseq = <&wifi_pwrseq>;
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
brcmf: wifi@1 {
reg = <1>;
compatible = "brcm,bcm4329-fmac";
pinctrl-names = "default";
pinctrl-0 = <&rtc_lsco_pins_a>;
};
};
/* Bluetooth */
&usart2 {
pinctrl-names = "default", "sleep", "idle";
pinctrl-0 = <&usart2_pins_c>;
pinctrl-1 = <&usart2_sleep_pins_c>;
pinctrl-2 = <&usart2_idle_pins_c>;
uart-has-rtscts;
status = "okay";
bluetooth {
shutdown-gpios = <&gpioz 6 GPIO_ACTIVE_HIGH>;
compatible = "brcm,bcm43438-bt";
max-speed = <3000000>;
vbat-supply = <&scmi_v3v3>;
vddio-supply = <&scmi_v3v3>;
};
};
/* Since I2C4 is disabled, STUSB1600 is also disabled so there is no Type-C support */
&usbotg_hs {
dr_mode = "peripheral";
role-switch-default-mode = "peripheral";
/*
* Forcing dr_mode = "peripheral"/"role-switch-default-mode = "peripheral";
* will cause the pull-up on D+/D- to be raised as soon as the OTG is configured at runtime,
* regardless of the presence of VBUS. Notice that on self-powered devices like
* stm32mp157f-dk2, this isn't compliant with the USB standard. That's why usbotg_hs is kept
* disabled here.
*/
status = "disabled";
};

17
arch/arm/boot/dts/st/stm32mp15xf.dtsi Normal file
View File

@@ -0,0 +1,17 @@
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
/*
* Copyright (C) STMicroelectronics 2025 - All Rights Reserved
* Author: Alexandre Torgue <alexandre.torgue@foss.st.com> for STMicroelectronics.
*/
&etzpc {
cryp1: cryp@54001000 {
compatible = "st,stm32mp1-cryp";
reg = <0x54001000 0x400>;
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc CRYP1>;
resets = <&rcc CRYP1_R>;
access-controllers = <&etzpc 9>;
status = "disabled";
};
};

3
arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi
View File

@@ -254,7 +254,7 @@ &i2c4 {
/delete-property/dmas;
/delete-property/dma-names;
stusb1600@28 {
stusb1600: typec@28 {
compatible = "st,stusb1600";
reg = <0x28>;
interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
@@ -515,6 +515,7 @@ sai2a_endpoint: endpoint {
remote-endpoint = <&cs42l51_tx_endpoint>;
dai-format = "i2s";
mclk-fs = <256>;
system-clock-direction-out;
dai-tdm-slot-num = <2>;
dai-tdm-slot-width = <32>;
};

61
arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi
View File

@@ -133,6 +133,53 @@ pins {
};
};
pwm3_pins_a: pwm3-0 {
pins {
pinmux = <STM32_PINMUX('B', 15, AF7)>; /* TIM3_CH2 */
bias-pull-down;
drive-push-pull;
slew-rate = <0>;
};
};
pwm3_sleep_pins_a: pwm3-sleep-0 {
pins {
pinmux = <STM32_PINMUX('B', 15, ANALOG)>; /* TIM3_CH2 */
};
};
pwm8_pins_a: pwm8-0 {
pins {
pinmux = <STM32_PINMUX('J', 5, AF8)>, /* TIM8_CH1 */
<STM32_PINMUX('J', 4, AF8)>; /* TIM8_CH4 */
bias-pull-down;
drive-push-pull;
slew-rate = <0>;
};
};
pwm8_sleep_pins_a: pwm8-sleep-0 {
pins {
pinmux = <STM32_PINMUX('J', 5, ANALOG)>, /* TIM8_CH1 */
<STM32_PINMUX('J', 4, ANALOG)>; /* TIM8_CH4 */
};
};
pwm12_pins_a: pwm12-0 {
pins {
pinmux = <STM32_PINMUX('B', 11, AF9)>; /* TIM12_CH2 */
bias-pull-down;
drive-push-pull;
slew-rate = <0>;
};
};
pwm12_sleep_pins_a: pwm12-sleep-0 {
pins {
pinmux = <STM32_PINMUX('B', 11, ANALOG)>; /* TIM12_CH2 */
};
};
sdmmc1_b4_pins_a: sdmmc1-b4-0 {
pins1 {
pinmux = <STM32_PINMUX('E', 4, AF10)>, /* SDMMC1_D0 */
@@ -209,6 +256,20 @@ pins1 {
};
};
tim10_counter_pins_a: tim10-counter-0 {
pins {
pinmux = <STM32_PINMUX('B', 9, AF9)>; /* TIM10_CH1 */
bias-disable;
};
};
tim10_counter_sleep_pins_a: tim10-counter-sleep-0 {
pins {
pinmux = <STM32_PINMUX('B', 9, ANALOG)>; /* TIM10_CH1 */
bias-disable;
};
};
usart2_pins_a: usart2-0 {
pins1 {
pinmux = <STM32_PINMUX('A', 4, AF6)>; /* USART2_TX */

527
arch/arm64/boot/dts/st/stm32mp251.dtsi
View File

@@ -150,7 +150,7 @@ timer {
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
always-on;
arm,no-tick-in-suspend;
};
soc@0 {
@@ -291,6 +291,273 @@ rifsc: bus@42080000 {
#access-controller-cells = <1>;
ranges;
timers2: timer@40000000 {
compatible = "st,stm32mp25-timers";
reg = <0x40000000 0x400>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "global";
clocks = <&rcc CK_KER_TIM2>;
clock-names = "int";
#address-cells = <1>;
#size-cells = <0>;
access-controllers = <&rifsc 1>;
power-domains = <&CLUSTER_PD>;
status = "disabled";
counter {
compatible = "st,stm32mp25-timer-counter";
status = "disabled";
};
pwm {
compatible = "st,stm32mp25-pwm";
#pwm-cells = <3>;
status = "disabled";
};
timer@1 {
compatible = "st,stm32mp25-timer-trigger";
reg = <1>;
status = "disabled";
};
};
timers3: timer@40010000 {
compatible = "st,stm32mp25-timers";
reg = <0x40010000 0x400>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "global";
clocks = <&rcc CK_KER_TIM3>;
clock-names = "int";
#address-cells = <1>;
#size-cells = <0>;
access-controllers = <&rifsc 2>;
power-domains = <&CLUSTER_PD>;
status = "disabled";
counter {
compatible = "st,stm32mp25-timer-counter";
status = "disabled";
};
pwm {
compatible = "st,stm32mp25-pwm";
#pwm-cells = <3>;
status = "disabled";
};
timer@2 {
compatible = "st,stm32mp25-timer-trigger";
reg = <2>;
status = "disabled";
};
};
timers4: timer@40020000 {
compatible = "st,stm32mp25-timers";
reg = <0x40020000 0x400>;
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "global";
clocks = <&rcc CK_KER_TIM4>;
clock-names = "int";
#address-cells = <1>;
#size-cells = <0>;
access-controllers = <&rifsc 3>;
power-domains = <&CLUSTER_PD>;
status = "disabled";
counter {
compatible = "st,stm32mp25-timer-counter";
status = "disabled";
};
pwm {
compatible = "st,stm32mp25-pwm";
#pwm-cells = <3>;
status = "disabled";
};
timer@3 {
compatible = "st,stm32mp25-timer-trigger";
reg = <3>;
status = "disabled";
};
};
timers5: timer@40030000 {
compatible = "st,stm32mp25-timers";
reg = <0x40030000 0x400>;
interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "global";
clocks = <&rcc CK_KER_TIM5>;
clock-names = "int";
#address-cells = <1>;
#size-cells = <0>;
access-controllers = <&rifsc 4>;
power-domains = <&CLUSTER_PD>;
status = "disabled";
counter {
compatible = "st,stm32mp25-timer-counter";
status = "disabled";
};
pwm {
compatible = "st,stm32mp25-pwm";
#pwm-cells = <3>;
status = "disabled";
};
timer@4 {
compatible = "st,stm32mp25-timer-trigger";
reg = <4>;
status = "disabled";
};
};
timers6: timer@40040000 {
compatible = "st,stm32mp25-timers";
reg = <0x40040000 0x400>;
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "global";
clocks = <&rcc CK_KER_TIM6>;
clock-names = "int";
#address-cells = <1>;
#size-cells = <0>;
access-controllers = <&rifsc 5>;
power-domains = <&CLUSTER_PD>;
status = "disabled";
counter {
compatible = "st,stm32mp25-timer-counter";
status = "disabled";
};
timer@5 {
compatible = "st,stm32mp25-timer-trigger";
reg = <5>;
status = "disabled";
};
};
timers7: timer@40050000 {
compatible = "st,stm32mp25-timers";
reg = <0x40050000 0x400>;
interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "global";
clocks = <&rcc CK_KER_TIM7>;
clock-names = "int";
#address-cells = <1>;
#size-cells = <0>;
access-controllers = <&rifsc 6>;
power-domains = <&CLUSTER_PD>;
status = "disabled";
counter {
compatible = "st,stm32mp25-timer-counter";
status = "disabled";
};
timer@6 {
compatible = "st,stm32mp25-timer-trigger";
reg = <6>;
status = "disabled";
};
};
timers12: timer@40060000 {
compatible = "st,stm32mp25-timers";
reg = <0x40060000 0x400>;
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "global";
clocks = <&rcc CK_KER_TIM12>;
clock-names = "int";
#address-cells = <1>;
#size-cells = <0>;
access-controllers = <&rifsc 10>;
power-domains = <&CLUSTER_PD>;
status = "disabled";
counter {
compatible = "st,stm32mp25-timer-counter";
status = "disabled";
};
pwm {
compatible = "st,stm32mp25-pwm";
#pwm-cells = <3>;
status = "disabled";
};
timer@11 {
compatible = "st,stm32mp25-timer-trigger";
reg = <11>;
status = "disabled";
};
};
timers13: timer@40070000 {
compatible = "st,stm32mp25-timers";
reg = <0x40070000 0x400>;
interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "global";
clocks = <&rcc CK_KER_TIM13>;
clock-names = "int";
#address-cells = <1>;
#size-cells = <0>;
access-controllers = <&rifsc 11>;
power-domains = <&CLUSTER_PD>;
status = "disabled";
counter {
compatible = "st,stm32mp25-timer-counter";
status = "disabled";
};
pwm {
compatible = "st,stm32mp25-pwm";
#pwm-cells = <3>;
status = "disabled";
};
timer@12 {
compatible = "st,stm32mp25-timer-trigger";
reg = <12>;
status = "disabled";
};
};
timers14: timer@40080000 {
compatible = "st,stm32mp25-timers";
reg = <0x40080000 0x400>;
interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "global";
clocks = <&rcc CK_KER_TIM14>;
clock-names = "int";
#address-cells = <1>;
#size-cells = <0>;
access-controllers = <&rifsc 12>;
power-domains = <&CLUSTER_PD>;
status = "disabled";
counter {
compatible = "st,stm32mp25-timer-counter";
status = "disabled";
};
pwm {
compatible = "st,stm32mp25-pwm";
#pwm-cells = <3>;
status = "disabled";
};
timer@13 {
compatible = "st,stm32mp25-timer-trigger";
reg = <13>;
status = "disabled";
};
};
lptimer1: timer@40090000 {
compatible = "st,stm32mp25-lptimer", "st,stm32-lptimer";
reg = <0x40090000 0x400>;
@@ -597,6 +864,136 @@ i2c7: i2c@40180000 {
status = "disabled";
};
timers10: timer@401c0000 {
compatible = "st,stm32mp25-timers";
reg = <0x401c0000 0x400>;
interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "global";
clocks = <&rcc CK_KER_TIM10>;
clock-names = "int";
#address-cells = <1>;
#size-cells = <0>;
access-controllers = <&rifsc 8>;
power-domains = <&CLUSTER_PD>;
status = "disabled";
counter {
compatible = "st,stm32mp25-timer-counter";
status = "disabled";
};
pwm {
compatible = "st,stm32mp25-pwm";
#pwm-cells = <3>;
status = "disabled";
};
timer@9 {
compatible = "st,stm32mp25-timer-trigger";
reg = <9>;
status = "disabled";
};
};
timers11: timer@401d0000 {
compatible = "st,stm32mp25-timers";
reg = <0x401d0000 0x400>;
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "global";
clocks = <&rcc CK_KER_TIM11>;
clock-names = "int";
#address-cells = <1>;
#size-cells = <0>;
access-controllers = <&rifsc 9>;
power-domains = <&CLUSTER_PD>;
status = "disabled";
counter {
compatible = "st,stm32mp25-timer-counter";
status = "disabled";
};
pwm {
compatible = "st,stm32mp25-pwm";
#pwm-cells = <3>;
status = "disabled";
};
timer@10 {
compatible = "st,stm32mp25-timer-trigger";
reg = <10>;
status = "disabled";
};
};
timers1: timer@40200000 {
compatible = "st,stm32mp25-timers";
reg = <0x40200000 0x400>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "brk", "up", "trg-com", "cc";
clocks = <&rcc CK_KER_TIM1>;
clock-names = "int";
#address-cells = <1>;
#size-cells = <0>;
access-controllers = <&rifsc 0>;
power-domains = <&CLUSTER_PD>;
status = "disabled";
counter {
compatible = "st,stm32mp25-timer-counter";
status = "disabled";
};
pwm {
compatible = "st,stm32mp25-pwm";
#pwm-cells = <3>;
status = "disabled";
};
timer@0 {
compatible = "st,stm32mp25-timer-trigger";
reg = <0>;
status = "disabled";
};
};
timers8: timer@40210000 {
compatible = "st,stm32mp25-timers";
reg = <0x40210000 0x400>;
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "brk", "up", "trg-com", "cc";
clocks = <&rcc CK_KER_TIM8>;
clock-names = "int";
#address-cells = <1>;
#size-cells = <0>;
access-controllers = <&rifsc 7>;
power-domains = <&CLUSTER_PD>;
status = "disabled";
counter {
compatible = "st,stm32mp25-timer-counter";
status = "disabled";
};
pwm {
compatible = "st,stm32mp25-pwm";
#pwm-cells = <3>;
status = "disabled";
};
timer@7 {
compatible = "st,stm32mp25-timer-trigger";
reg = <7>;
status = "disabled";
};
};
usart6: serial@40220000 {
compatible = "st,stm32h7-uart";
reg = <0x40220000 0x400>;
@@ -654,6 +1051,99 @@ spi4: spi@40240000 {
status = "disabled";
};
timers15: timer@40250000 {
compatible = "st,stm32mp25-timers";
reg = <0x40250000 0x400>;
interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "global";
clocks = <&rcc CK_KER_TIM15>;
clock-names = "int";
#address-cells = <1>;
#size-cells = <0>;
access-controllers = <&rifsc 13>;
power-domains = <&CLUSTER_PD>;
status = "disabled";
counter {
compatible = "st,stm32mp25-timer-counter";
status = "disabled";
};
pwm {
compatible = "st,stm32mp25-pwm";
#pwm-cells = <3>;
status = "disabled";
};
timer@14 {
compatible = "st,stm32mp25-timer-trigger";
reg = <14>;
status = "disabled";
};
};
timers16: timer@40260000 {
compatible = "st,stm32mp25-timers";
reg = <0x40260000 0x400>;
interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "global";
clocks = <&rcc CK_KER_TIM16>;
clock-names = "int";
#address-cells = <1>;
#size-cells = <0>;
access-controllers = <&rifsc 14>;
power-domains = <&CLUSTER_PD>;
status = "disabled";
counter {
compatible = "st,stm32mp25-timer-counter";
status = "disabled";
};
pwm {
compatible = "st,stm32mp25-pwm";
#pwm-cells = <3>;
status = "disabled";
};
timer@15 {
compatible = "st,stm32mp25-timer-trigger";
reg = <15>;
status = "disabled";
};
};
timers17: timer@40270000 {
compatible = "st,stm32mp25-timers";
reg = <0x40270000 0x400>;
interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "global";
clocks = <&rcc CK_KER_TIM17>;
clock-names = "int";
#address-cells = <1>;
#size-cells = <0>;
access-controllers = <&rifsc 15>;
power-domains = <&CLUSTER_PD>;
status = "disabled";
counter {
compatible = "st,stm32mp25-timer-counter";
status = "disabled";
};
pwm {
compatible = "st,stm32mp25-pwm";
#pwm-cells = <3>;
status = "disabled";
};
timer@16 {
compatible = "st,stm32mp25-timer-trigger";
reg = <16>;
status = "disabled";
};
};
spi5: spi@40280000 {
#address-cells = <1>;
#size-cells = <0>;
@@ -783,6 +1273,40 @@ uart9: serial@402c0000 {
status = "disabled";
};
timers20: timer@40320000 {
compatible = "st,stm32mp25-timers";
reg = <0x40320000 0x400>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "brk", "up", "trg-com", "cc";
clocks = <&rcc CK_KER_TIM20>;
clock-names = "int";
#address-cells = <1>;
#size-cells = <0>;
access-controllers = <&rifsc 16>;
power-domains = <&CLUSTER_PD>;
status = "disabled";
counter {
compatible = "st,stm32mp25-timer-counter";
status = "disabled";
};
pwm {
compatible = "st,stm32mp25-pwm";
#pwm-cells = <3>;
status = "disabled";
};
timer@19 {
compatible = "st,stm32mp25-timer-trigger";
reg = <19>;
status = "disabled";
};
};
usart1: serial@40330000 {
compatible = "st,stm32h7-uart";
reg = <0x40330000 0x400>;
@@ -1495,7 +2019,6 @@ gpioz: gpio@46200000 {
st,bank-ioport = <11>;
status = "disabled";
};
};
exti2: interrupt-controller@46230000 {

58
arch/arm64/boot/dts/st/stm32mp257f-ev1.dts
View File

@@ -293,6 +293,64 @@ &spi8 {
status = "disabled";
};
&timers3 {
status = "disabled";
counter {
status = "okay";
};
pwm {
pinctrl-0 = <&pwm3_pins_a>;
pinctrl-1 = <&pwm3_sleep_pins_a>;
pinctrl-names = "default", "sleep";
status = "okay";
};
timer@2 {
status = "okay";
};
};
&timers8 {
status = "disabled";
counter {
status = "okay";
};
pwm {
pinctrl-0 = <&pwm8_pins_a>;
pinctrl-1 = <&pwm8_sleep_pins_a>;
pinctrl-names = "default", "sleep";
status = "okay";
};
timer@7 {
status = "okay";
};
};
&timers10 {
status = "disabled";
counter {
pinctrl-0 = <&tim10_counter_pins_a>;
pinctrl-1 = <&tim10_counter_sleep_pins_a>;
pinctrl-names = "default", "sleep";
status = "okay";
};
};
&timers12 {
status = "disabled";
counter {
status = "okay";
};
pwm {
pinctrl-0 = <&pwm12_pins_a>;
pinctrl-1 = <&pwm12_sleep_pins_a>;
pinctrl-names = "default", "sleep";
status = "okay";
};
timer@11 {
status = "okay";
};
};
&usart2 {
pinctrl-names = "default", "idle", "sleep";
pinctrl-0 = <&usart2_pins_a>;

6
arch/arm64/configs/defconfig
View File

@@ -581,6 +581,7 @@ CONFIG_SPI_QUP=y
CONFIG_SPI_QCOM_GENI=m
CONFIG_SPI_S3C64XX=y
CONFIG_SPI_SH_MSIOF=m
CONFIG_SPI_STM32_OSPI=m
CONFIG_SPI_SUN6I=y
CONFIG_SPI_TEGRA210_QUAD=m
CONFIG_SPI_TEGRA114=m
@@ -783,6 +784,7 @@ CONFIG_MFD_TPS65219=y
CONFIG_MFD_TPS6594_I2C=m
CONFIG_MFD_ROHM_BD718XX=y
CONFIG_MFD_STM32_LPTIMER=m
CONFIG_MFD_STM32_TIMERS=m
CONFIG_MFD_WCD934X=m
CONFIG_MFD_KHADAS_MCU=m
CONFIG_REGULATOR_FIXED_VOLTAGE=y
@@ -1519,6 +1521,7 @@ CONFIG_EXTCON_USB_GPIO=y
CONFIG_EXTCON_USBC_CROS_EC=y
CONFIG_FSL_IFC=y
CONFIG_RENESAS_RPCIF=m
CONFIG_STM32_OMM=m
CONFIG_IIO=y
CONFIG_EXYNOS_ADC=y
CONFIG_IMX8QXP_ADC=m
@@ -1539,6 +1542,7 @@ CONFIG_IIO_CROS_EC_LIGHT_PROX=m
CONFIG_SENSORS_ISL29018=m
CONFIG_VCNL4000=m
CONFIG_IIO_ST_MAGN_3AXIS=m
CONFIG_IIO_STM32_TIMER_TRIGGER=m
CONFIG_IIO_CROS_EC_BARO=m
CONFIG_MPL3115=m
CONFIG_PWM=y
@@ -1557,6 +1561,7 @@ CONFIG_PWM_RENESAS_TPU=m
CONFIG_PWM_ROCKCHIP=y
CONFIG_PWM_SAMSUNG=y
CONFIG_PWM_SL28CPLD=m
CONFIG_PWM_STM32=m
CONFIG_PWM_SUN4I=m
CONFIG_PWM_TEGRA=m
CONFIG_PWM_TIECAP=m
@@ -1703,6 +1708,7 @@ CONFIG_INTERCONNECT_QCOM_X1E80100=y
CONFIG_COUNTER=m
CONFIG_TI_EQEP=m
CONFIG_RZ_MTU3_CNT=m
CONFIG_STM32_TIMER_CNT=m
CONFIG_HTE=y
CONFIG_HTE_TEGRA194=y
CONFIG_HTE_TEGRA194_TEST=m

40
include/dt-bindings/regulator/st,stm32mp15-regulator.h Normal file
View File

@@ -0,0 +1,40 @@
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
/*
* Copyright (C) 2025, STMicroelectronics - All Rights Reserved
*/
#ifndef __DT_BINDINGS_REGULATOR_ST_STM32MP15_REGULATOR_H
#define __DT_BINDINGS_REGULATOR_ST_STM32MP15_REGULATOR_H
/* SCMI voltage domain identifiers */
/* SOC Internal regulators */
#define VOLTD_SCMI_REG11 0
#define VOLTD_SCMI_REG18 1
#define VOLTD_SCMI_USB33 2
/* STPMIC1 regulators */
#define VOLTD_SCMI_STPMIC1_BUCK1 3
#define VOLTD_SCMI_STPMIC1_BUCK2 4
#define VOLTD_SCMI_STPMIC1_BUCK3 5
#define VOLTD_SCMI_STPMIC1_BUCK4 6
#define VOLTD_SCMI_STPMIC1_LDO1 7
#define VOLTD_SCMI_STPMIC1_LDO2 8
#define VOLTD_SCMI_STPMIC1_LDO3 9
#define VOLTD_SCMI_STPMIC1_LDO4 10
#define VOLTD_SCMI_STPMIC1_LDO5 11
#define VOLTD_SCMI_STPMIC1_LDO6 12
#define VOLTD_SCMI_STPMIC1_VREFDDR 13
#define VOLTD_SCMI_STPMIC1_BOOST 14
#define VOLTD_SCMI_STPMIC1_PWR_SW1 15
#define VOLTD_SCMI_STPMIC1_PWR_SW2 16
#define VOLTD_SCMI_VREFBUF 17
/* External regulators */
#define VOLTD_SCMI_REGU0 18
#define VOLTD_SCMI_REGU1 19
#define VOLTD_SCMI_REGU2 20
#define VOLTD_SCMI_REGU3 21
#define VOLTD_SCMI_REGU4 22
#endif /*__DT_BINDINGS_REGULATOR_ST_STM32MP15_REGULATOR_H */