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drm/nouveau/mspdec: switch to instanced constructor

Browse Source 
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
This commit is contained in:
Ben Skeggs
2021-02-04 08:38:32 +10:00
parent e9e9a219e4
commit 963216061c
15 changed files with 47 additions and 51 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/drm/nouveau/include/nvkm/core/device.h
View File

@@ -60,7 +60,6 @@ struct nvkm_device {
struct notifier_block nb;
} acpi;
struct nvkm_engine *mspdec;
struct nvkm_engine *msppp;
struct nvkm_engine *msvld;
struct nvkm_nvenc *nvenc[3];
@@ -111,7 +110,6 @@ struct nvkm_device_chip {
#undef NVKM_LAYOUT_INST
#undef NVKM_LAYOUT_ONCE
int (*mspdec )(struct nvkm_device *, int idx, struct nvkm_engine **);
int (*msppp )(struct nvkm_device *, int idx, struct nvkm_engine **);
int (*msvld )(struct nvkm_device *, int idx, struct nvkm_engine **);
int (*nvenc[3])(struct nvkm_device *, int idx, struct nvkm_nvenc **);

1
drivers/gpu/drm/nouveau/include/nvkm/core/layout.h
View File

@@ -36,4 +36,5 @@ NVKM_LAYOUT_ONCE(NVKM_ENGINE_IFB , struct nvkm_engine , ifb)
NVKM_LAYOUT_ONCE(NVKM_ENGINE_ME , struct nvkm_engine , me)
NVKM_LAYOUT_ONCE(NVKM_ENGINE_MPEG , struct nvkm_engine , mpeg)
NVKM_LAYOUT_ONCE(NVKM_ENGINE_MSENC , struct nvkm_engine , msenc)
NVKM_LAYOUT_ONCE(NVKM_ENGINE_MSPDEC , struct nvkm_engine , mspdec)
NVKM_LAYOUT_ONCE(NVKM_ENGINE_VP , struct nvkm_engine , vp)

8
drivers/gpu/drm/nouveau/include/nvkm/engine/mspdec.h
View File

@@ -2,8 +2,8 @@
#ifndef __NVKM_MSPDEC_H__
#define __NVKM_MSPDEC_H__
#include <engine/falcon.h>
int g98_mspdec_new(struct nvkm_device *, int, struct nvkm_engine **);
int gt215_mspdec_new(struct nvkm_device *, int, struct nvkm_engine **);
int gf100_mspdec_new(struct nvkm_device *, int, struct nvkm_engine **);
int gk104_mspdec_new(struct nvkm_device *, int, struct nvkm_engine **);
int g98_mspdec_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);
int gt215_mspdec_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);
int gf100_mspdec_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);
int gk104_mspdec_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_engine **);
#endif

1
drivers/gpu/drm/nouveau/nvkm/core/subdev.c
View File

@@ -33,7 +33,6 @@ nvkm_subdev_type[NVKM_SUBDEV_NR] = {
#include <core/layout.h>
#undef NVKM_LAYOUT_ONCE
#undef NVKM_LAYOUT_INST
[NVKM_ENGINE_MSPDEC ] = "mspdec",
[NVKM_ENGINE_MSPPP ] = "msppp",
[NVKM_ENGINE_MSVLD ] = "msvld",
[NVKM_ENGINE_NVENC0 ] = "nvenc0",

47
drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
View File

@@ -1098,7 +1098,7 @@ nv98_chipset = {
.dma = { 0x00000001, nv50_dma_new },
.fifo = { 0x00000001, g84_fifo_new },
.gr = { 0x00000001, g84_gr_new },
.mspdec = g98_mspdec_new,
.mspdec = { 0x00000001, g98_mspdec_new },
.msppp = g98_msppp_new,
.msvld = g98_msvld_new,
.pm = g84_pm_new,
@@ -1165,7 +1165,7 @@ nva3_chipset = {
.fifo = { 0x00000001, g84_fifo_new },
.gr = { 0x00000001, gt215_gr_new },
.mpeg = { 0x00000001, g84_mpeg_new },
.mspdec = gt215_mspdec_new,
.mspdec = { 0x00000001, gt215_mspdec_new },
.msppp = gt215_msppp_new,
.msvld = gt215_msvld_new,
.pm = gt215_pm_new,
@@ -1198,7 +1198,7 @@ nva5_chipset = {
.dma = { 0x00000001, nv50_dma_new },
.fifo = { 0x00000001, g84_fifo_new },
.gr = { 0x00000001, gt215_gr_new },
.mspdec = gt215_mspdec_new,
.mspdec = { 0x00000001, gt215_mspdec_new },
.msppp = gt215_msppp_new,
.msvld = gt215_msvld_new,
.pm = gt215_pm_new,
@@ -1231,7 +1231,7 @@ nva8_chipset = {
.dma = { 0x00000001, nv50_dma_new },
.fifo = { 0x00000001, g84_fifo_new },
.gr = { 0x00000001, gt215_gr_new },
.mspdec = gt215_mspdec_new,
.mspdec = { 0x00000001, gt215_mspdec_new },
.msppp = gt215_msppp_new,
.msvld = gt215_msvld_new,
.pm = gt215_pm_new,
@@ -1262,7 +1262,7 @@ nvaa_chipset = {
.dma = { 0x00000001, nv50_dma_new },
.fifo = { 0x00000001, g84_fifo_new },
.gr = { 0x00000001, gt200_gr_new },
.mspdec = g98_mspdec_new,
.mspdec = { 0x00000001, g98_mspdec_new },
.msppp = g98_msppp_new,
.msvld = g98_msvld_new,
.pm = g84_pm_new,
@@ -1294,7 +1294,7 @@ nvac_chipset = {
.dma = { 0x00000001, nv50_dma_new },
.fifo = { 0x00000001, g84_fifo_new },
.gr = { 0x00000001, mcp79_gr_new },
.mspdec = g98_mspdec_new,
.mspdec = { 0x00000001, g98_mspdec_new },
.msppp = g98_msppp_new,
.msvld = g98_msvld_new,
.pm = g84_pm_new,
@@ -1328,7 +1328,7 @@ nvaf_chipset = {
.dma = { 0x00000001, nv50_dma_new },
.fifo = { 0x00000001, g84_fifo_new },
.gr = { 0x00000001, mcp89_gr_new },
.mspdec = gt215_mspdec_new,
.mspdec = { 0x00000001, gt215_mspdec_new },
.msppp = gt215_msppp_new,
.msvld = mcp89_msvld_new,
.pm = gt215_pm_new,
@@ -1364,7 +1364,7 @@ nvc0_chipset = {
.dma = { 0x00000001, gf100_dma_new },
.fifo = { 0x00000001, gf100_fifo_new },
.gr = { 0x00000001, gf100_gr_new },
.mspdec = gf100_mspdec_new,
.mspdec = { 0x00000001, gf100_mspdec_new },
.msppp = gf100_msppp_new,
.msvld = gf100_msvld_new,
.pm = gf100_pm_new,
@@ -1400,7 +1400,7 @@ nvc1_chipset = {
.dma = { 0x00000001, gf100_dma_new },
.fifo = { 0x00000001, gf100_fifo_new },
.gr = { 0x00000001, gf108_gr_new },
.mspdec = gf100_mspdec_new,
.mspdec = { 0x00000001, gf100_mspdec_new },
.msppp = gf100_msppp_new,
.msvld = gf100_msvld_new,
.pm = gf108_pm_new,
@@ -1436,7 +1436,7 @@ nvc3_chipset = {
.dma = { 0x00000001, gf100_dma_new },
.fifo = { 0x00000001, gf100_fifo_new },
.gr = { 0x00000001, gf104_gr_new },
.mspdec = gf100_mspdec_new,
.mspdec = { 0x00000001, gf100_mspdec_new },
.msppp = gf100_msppp_new,
.msvld = gf100_msvld_new,
.pm = gf100_pm_new,
@@ -1472,7 +1472,7 @@ nvc4_chipset = {
.dma = { 0x00000001, gf100_dma_new },
.fifo = { 0x00000001, gf100_fifo_new },
.gr = { 0x00000001, gf104_gr_new },
.mspdec = gf100_mspdec_new,
.mspdec = { 0x00000001, gf100_mspdec_new },
.msppp = gf100_msppp_new,
.msvld = gf100_msvld_new,
.pm = gf100_pm_new,
@@ -1508,7 +1508,7 @@ nvc8_chipset = {
.dma = { 0x00000001, gf100_dma_new },
.fifo = { 0x00000001, gf100_fifo_new },
.gr = { 0x00000001, gf110_gr_new },
.mspdec = gf100_mspdec_new,
.mspdec = { 0x00000001, gf100_mspdec_new },
.msppp = gf100_msppp_new,
.msvld = gf100_msvld_new,
.pm = gf100_pm_new,
@@ -1544,7 +1544,7 @@ nvce_chipset = {
.dma = { 0x00000001, gf100_dma_new },
.fifo = { 0x00000001, gf100_fifo_new },
.gr = { 0x00000001, gf104_gr_new },
.mspdec = gf100_mspdec_new,
.mspdec = { 0x00000001, gf100_mspdec_new },
.msppp = gf100_msppp_new,
.msvld = gf100_msvld_new,
.pm = gf100_pm_new,
@@ -1580,7 +1580,7 @@ nvcf_chipset = {
.dma = { 0x00000001, gf100_dma_new },
.fifo = { 0x00000001, gf100_fifo_new },
.gr = { 0x00000001, gf104_gr_new },
.mspdec = gf100_mspdec_new,
.mspdec = { 0x00000001, gf100_mspdec_new },
.msppp = gf100_msppp_new,
.msvld = gf100_msvld_new,
.pm = gf100_pm_new,
@@ -1615,7 +1615,7 @@ nvd7_chipset = {
.dma = { 0x00000001, gf119_dma_new },
.fifo = { 0x00000001, gf100_fifo_new },
.gr = { 0x00000001, gf117_gr_new },
.mspdec = gf100_mspdec_new,
.mspdec = { 0x00000001, gf100_mspdec_new },
.msppp = gf100_msppp_new,
.msvld = gf100_msvld_new,
.pm = gf117_pm_new,
@@ -1651,7 +1651,7 @@ nvd9_chipset = {
.dma = { 0x00000001, gf119_dma_new },
.fifo = { 0x00000001, gf100_fifo_new },
.gr = { 0x00000001, gf119_gr_new },
.mspdec = gf100_mspdec_new,
.mspdec = { 0x00000001, gf100_mspdec_new },
.msppp = gf100_msppp_new,
.msvld = gf100_msvld_new,
.pm = gf117_pm_new,
@@ -1688,7 +1688,7 @@ nve4_chipset = {
.dma = { 0x00000001, gf119_dma_new },
.fifo = { 0x00000001, gk104_fifo_new },
.gr = { 0x00000001, gk104_gr_new },
.mspdec = gk104_mspdec_new,
.mspdec = { 0x00000001, gk104_mspdec_new },
.msppp = gf100_msppp_new,
.msvld = gk104_msvld_new,
.pm = gk104_pm_new,
@@ -1725,7 +1725,7 @@ nve6_chipset = {
.dma = { 0x00000001, gf119_dma_new },
.fifo = { 0x00000001, gk104_fifo_new },
.gr = { 0x00000001, gk104_gr_new },
.mspdec = gk104_mspdec_new,
.mspdec = { 0x00000001, gk104_mspdec_new },
.msppp = gf100_msppp_new,
.msvld = gk104_msvld_new,
.pm = gk104_pm_new,
@@ -1762,7 +1762,7 @@ nve7_chipset = {
.dma = { 0x00000001, gf119_dma_new },
.fifo = { 0x00000001, gk104_fifo_new },
.gr = { 0x00000001, gk104_gr_new },
.mspdec = gk104_mspdec_new,
.mspdec = { 0x00000001, gk104_mspdec_new },
.msppp = gf100_msppp_new,
.msvld = gk104_msvld_new,
.pm = gk104_pm_new,
@@ -1824,7 +1824,7 @@ nvf0_chipset = {
.dma = { 0x00000001, gf119_dma_new },
.fifo = { 0x00000001, gk110_fifo_new },
.gr = { 0x00000001, gk110_gr_new },
.mspdec = gk104_mspdec_new,
.mspdec = { 0x00000001, gk104_mspdec_new },
.msppp = gf100_msppp_new,
.msvld = gk104_msvld_new,
.sw = gf100_sw_new,
@@ -1860,7 +1860,7 @@ nvf1_chipset = {
.dma = { 0x00000001, gf119_dma_new },
.fifo = { 0x00000001, gk110_fifo_new },
.gr = { 0x00000001, gk110b_gr_new },
.mspdec = gk104_mspdec_new,
.mspdec = { 0x00000001, gk104_mspdec_new },
.msppp = gf100_msppp_new,
.msvld = gk104_msvld_new,
.sw = gf100_sw_new,
@@ -1896,7 +1896,7 @@ nv106_chipset = {
.dma = { 0x00000001, gf119_dma_new },
.fifo = { 0x00000001, gk208_fifo_new },
.gr = { 0x00000001, gk208_gr_new },
.mspdec = gk104_mspdec_new,
.mspdec = { 0x00000001, gk104_mspdec_new },
.msppp = gf100_msppp_new,
.msvld = gk104_msvld_new,
.sw = gf100_sw_new,
@@ -1932,7 +1932,7 @@ nv108_chipset = {
.dma = { 0x00000001, gf119_dma_new },
.fifo = { 0x00000001, gk208_fifo_new },
.gr = { 0x00000001, gk208_gr_new },
.mspdec = gk104_mspdec_new,
.mspdec = { 0x00000001, gk104_mspdec_new },
.msppp = gf100_msppp_new,
.msvld = gk104_msvld_new,
.sw = gf100_sw_new,
@@ -3174,7 +3174,6 @@ nvkm_device_ctor(const struct nvkm_device_func *func,
#include <core/layout.h>
#undef NVKM_LAYOUT_INST
#undef NVKM_LAYOUT_ONCE
_(NVKM_ENGINE_MSPDEC , mspdec);
_(NVKM_ENGINE_MSPPP , msppp);
_(NVKM_ENGINE_MSVLD , msvld);
_(NVKM_ENGINE_NVENC0 , nvenc[0]);

7
drivers/gpu/drm/nouveau/nvkm/engine/mspdec/base.c
View File

@@ -24,9 +24,8 @@
#include "priv.h"
int
nvkm_mspdec_new_(const struct nvkm_falcon_func *func,
struct nvkm_device *device, int index,
struct nvkm_engine **pengine)
nvkm_mspdec_new_(const struct nvkm_falcon_func *func, struct nvkm_device *device,
enum nvkm_subdev_type type, int inst, struct nvkm_engine **pengine)
{
return nvkm_falcon_new_(func, device, index, true, 0x085000, pengine);
return nvkm_falcon_new_(func, device, type, inst, true, 0x085000, pengine);
}

6
drivers/gpu/drm/nouveau/nvkm/engine/mspdec/g98.c
View File

@@ -43,8 +43,8 @@ g98_mspdec = {
};
int
g98_mspdec_new(struct nvkm_device *device, int index,
struct nvkm_engine **pengine)
g98_mspdec_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_engine **pengine)
{
return nvkm_mspdec_new_(&g98_mspdec, device, index, pengine);
return nvkm_mspdec_new_(&g98_mspdec, device, type, inst, pengine);
}

4
drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gf100.c
View File

@@ -43,8 +43,8 @@ gf100_mspdec = {
};
int
gf100_mspdec_new(struct nvkm_device *device, int index,
gf100_mspdec_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_engine **pengine)
{
return nvkm_mspdec_new_(&gf100_mspdec, device, index, pengine);
return nvkm_mspdec_new_(&gf100_mspdec, device, type, inst, pengine);
}

4
drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gk104.c
View File

@@ -35,8 +35,8 @@ gk104_mspdec = {
};
int
gk104_mspdec_new(struct nvkm_device *device, int index,
gk104_mspdec_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_engine **pengine)
{
return nvkm_mspdec_new_(&gk104_mspdec, device, index, pengine);
return nvkm_mspdec_new_(&gk104_mspdec, device, type, inst, pengine);
}

6
drivers/gpu/drm/nouveau/nvkm/engine/mspdec/gt215.c
View File

@@ -35,8 +35,8 @@ gt215_mspdec = {
};
int
gt215_mspdec_new(struct nvkm_device *device, int index,
struct nvkm_engine **pengine)
gt215_mspdec_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
struct nvkm_engine **pengine)
{
return nvkm_mspdec_new_(&gt215_mspdec, device, index, pengine);
return nvkm_mspdec_new_(&gt215_mspdec, device, type, inst, pengine);
}

4
drivers/gpu/drm/nouveau/nvkm/engine/mspdec/priv.h
View File

@@ -3,8 +3,8 @@
#define __NVKM_MSPDEC_PRIV_H__
#include <engine/mspdec.h>
int nvkm_mspdec_new_(const struct nvkm_falcon_func *, struct nvkm_device *,
int index, struct nvkm_engine **);
int nvkm_mspdec_new_(const struct nvkm_falcon_func *, struct nvkm_device *, enum nvkm_subdev_type,
int, struct nvkm_engine **);
void g98_mspdec_init(struct nvkm_falcon *);

2
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g98.c
View File

@@ -35,7 +35,7 @@ g98_devinit_disable(struct nvkm_devinit *init)
u64 disable = 0ULL;
if (!(r001540 & 0x40000000)) {
disable |= (1ULL << NVKM_ENGINE_MSPDEC);
nvkm_subdev_disable(device, NVKM_ENGINE_MSPDEC, 0);
disable |= (1ULL << NVKM_ENGINE_MSVLD);
disable |= (1ULL << NVKM_ENGINE_MSPPP);
}

2
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gf100.c
View File

@@ -74,7 +74,7 @@ gf100_devinit_disable(struct nvkm_devinit *init)
nvkm_subdev_disable(device, NVKM_ENGINE_DISP, 0);
if (r022500 & 0x00000002) {
disable |= (1ULL << NVKM_ENGINE_MSPDEC);
nvkm_subdev_disable(device, NVKM_ENGINE_MSPDEC, 0);
disable |= (1ULL << NVKM_ENGINE_MSPPP);
}

2
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gt215.c
View File

@@ -71,7 +71,7 @@ gt215_devinit_disable(struct nvkm_devinit *init)
u64 disable = 0ULL;
if (!(r001540 & 0x40000000)) {
disable |= (1ULL << NVKM_ENGINE_MSPDEC);
nvkm_subdev_disable(device, NVKM_ENGINE_MSPDEC, 0);
disable |= (1ULL << NVKM_ENGINE_MSPPP);
}

2
drivers/gpu/drm/nouveau/nvkm/subdev/devinit/mcp89.c
View File

@@ -35,7 +35,7 @@ mcp89_devinit_disable(struct nvkm_devinit *init)
u64 disable = 0;
if (!(r001540 & 0x40000000)) {
disable |= (1ULL << NVKM_ENGINE_MSPDEC);
nvkm_subdev_disable(device, NVKM_ENGINE_MSPDEC, 0);
disable |= (1ULL << NVKM_ENGINE_MSPPP);
}