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drm/i915/uc: Fix undefined behavior due to shift overflowing the constant
Fix:
In file included from <command-line>:0:0:
drivers/gpu/drm/i915/gt/uc/intel_guc.c: In function ‘intel_guc_send_mmio’:
././include/linux/compiler_types.h:352:38: error: call to ‘__compiletime_assert_1047’ \
declared with attribute error: FIELD_PREP: mask is not constant
_compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
and other build errors due to shift overflowing values.
See https://lore.kernel.org/r/YkwQ6%2BtIH8GQpuct@zn.tnic for the gory
details as to why it triggers with older gccs only.
v2 by Jani:
- Drop the i915_reg.h changes
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Ruiqi GONG <gongruiqi1@huawei.com>
Cc: Randy Dunlap <rdunlap@infradead.org>
Signed-off-by: Borislav Petkov <bp@suse.de>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220518113315.1305027-2-jani.nikula@intel.com
This commit is contained in:
committed by
Jani Nikula
parent
1ade30812a
commit
962bd34bb4
@@ -50,7 +50,7 @@
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#define HOST2GUC_SELF_CFG_REQUEST_MSG_LEN (GUC_HXG_REQUEST_MSG_MIN_LEN + 3u)
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#define HOST2GUC_SELF_CFG_REQUEST_MSG_0_MBZ GUC_HXG_REQUEST_MSG_0_DATA0
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#define HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_KEY (0xffff << 16)
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#define HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_KEY (0xffffU << 16)
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#define HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_LEN (0xffff << 0)
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#define HOST2GUC_SELF_CFG_REQUEST_MSG_2_VALUE32 GUC_HXG_REQUEST_MSG_n_DATAn
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#define HOST2GUC_SELF_CFG_REQUEST_MSG_3_VALUE64 GUC_HXG_REQUEST_MSG_n_DATAn
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@@ -82,7 +82,7 @@ static_assert(sizeof(struct guc_ct_buffer_desc) == 64);
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#define GUC_CTB_HDR_LEN 1u
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#define GUC_CTB_MSG_MIN_LEN GUC_CTB_HDR_LEN
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#define GUC_CTB_MSG_MAX_LEN 256u
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#define GUC_CTB_MSG_0_FENCE (0xffff << 16)
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#define GUC_CTB_MSG_0_FENCE (0xffffU << 16)
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#define GUC_CTB_MSG_0_FORMAT (0xf << 12)
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#define GUC_CTB_FORMAT_HXG 0u
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#define GUC_CTB_MSG_0_RESERVED (0xf << 8)
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@@ -40,7 +40,7 @@
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*/
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#define GUC_HXG_MSG_MIN_LEN 1u
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#define GUC_HXG_MSG_0_ORIGIN (0x1 << 31)
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#define GUC_HXG_MSG_0_ORIGIN (0x1U << 31)
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#define GUC_HXG_ORIGIN_HOST 0u
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#define GUC_HXG_ORIGIN_GUC 1u
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#define GUC_HXG_MSG_0_TYPE (0x7 << 28)
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@@ -28,7 +28,7 @@
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#define GS_MIA_HALT_REQUESTED (0x02 << GS_MIA_SHIFT)
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#define GS_MIA_ISR_ENTRY (0x04 << GS_MIA_SHIFT)
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#define GS_AUTH_STATUS_SHIFT 30
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#define GS_AUTH_STATUS_MASK (0x03 << GS_AUTH_STATUS_SHIFT)
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#define GS_AUTH_STATUS_MASK (0x03U << GS_AUTH_STATUS_SHIFT)
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#define GS_AUTH_STATUS_BAD (0x01 << GS_AUTH_STATUS_SHIFT)
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#define GS_AUTH_STATUS_GOOD (0x02 << GS_AUTH_STATUS_SHIFT)
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