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arm64: dts: renesas: r8a779g0: Add display related nodes

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Add DT nodes for components needed to get the DSI output working:
- FCPv
- VSPd
- DU
- DSI

Signed-off-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com>
Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20221201095631.89448-5-tomi.valkeinen+renesas@ideasonboard.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Tomi Valkeinen
2022-12-01 11:56:28 +02:00
committed by Geert Uytterhoeven
parent ef10e647d9
commit 95d60f13d3
1 changed files with 130 additions and 0 deletions
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130
arch/arm64/boot/dts/renesas/r8a779g0.dtsi
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@@ -1203,6 +1203,136 @@ gic: interrupt-controller@f1000000 {
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
};
fcpvd0: fcp@fea10000 {
compatible = "renesas,fcpv";
reg = <0 0xfea10000 0 0x200>;
clocks = <&cpg CPG_MOD 508>;
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 508>;
};
fcpvd1: fcp@fea11000 {
compatible = "renesas,fcpv";
reg = <0 0xfea11000 0 0x200>;
clocks = <&cpg CPG_MOD 509>;
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 509>;
};
vspd0: vsp@fea20000 {
compatible = "renesas,vsp2";
reg = <0 0xfea20000 0 0x7000>;
interrupts = <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 830>;
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 830>;
renesas,fcp = <&fcpvd0>;
};
vspd1: vsp@fea28000 {
compatible = "renesas,vsp2";
reg = <0 0xfea28000 0 0x7000>;
interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 831>;
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 831>;
renesas,fcp = <&fcpvd1>;
};
du: display@feb00000 {
compatible = "renesas,du-r8a779g0";
reg = <0 0xfeb00000 0 0x40000>;
interrupts = <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cpg CPG_MOD 411>;
clock-names = "du.0";
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 411>;
reset-names = "du.0";
renesas,vsps = <&vspd0 0>, <&vspd1 0>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
du_out_dsi0: endpoint {
remote-endpoint = <&dsi0_in>;
};
};
port@1 {
reg = <1>;
du_out_dsi1: endpoint {
remote-endpoint = <&dsi1_in>;
};
};
};
};
dsi0: dsi-encoder@fed80000 {
compatible = "renesas,r8a779g0-dsi-csi2-tx";
reg = <0 0xfed80000 0 0x10000>;
clocks = <&cpg CPG_MOD 415>,
<&cpg CPG_CORE R8A779G0_CLK_DSIEXT>,
<&cpg CPG_CORE R8A779G0_CLK_DSIREF>;
clock-names = "fck", "dsi", "pll";
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 415>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi0_in: endpoint {
remote-endpoint = <&du_out_dsi0>;
};
};
port@1 {
reg = <1>;
};
};
};
dsi1: dsi-encoder@fed90000 {
compatible = "renesas,r8a779g0-dsi-csi2-tx";
reg = <0 0xfed90000 0 0x10000>;
clocks = <&cpg CPG_MOD 416>,
<&cpg CPG_CORE R8A779G0_CLK_DSIEXT>,
<&cpg CPG_CORE R8A779G0_CLK_DSIREF>;
clock-names = "fck", "dsi", "pll";
power-domains = <&sysc R8A779G0_PD_ALWAYS_ON>;
resets = <&cpg 416>;
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi1_in: endpoint {
remote-endpoint = <&du_out_dsi1>;
};
};
port@1 {
reg = <1>;
};
};
};
prr: chipid@fff00044 {
compatible = "renesas,prr";
reg = <0 0xfff00044 0 4>;