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dt-bindings: i3c: Add Renesas I3C controller
Add Renesas I3C controller which is available in R9A08G045 (RZ/G3S) and R9A09G047 (RZ/G3E) SoCs. Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20250724094146.6443-4-wsa+renesas@sang-engineering.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
This commit is contained in:
Tommaso Merciai
committed by
Alexandre Belloni
Alexandre Belloni
parent
8acf1f3bae
commit
94e611b5b9
179
Documentation/devicetree/bindings/i3c/renesas,i3c.yaml
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179
Documentation/devicetree/bindings/i3c/renesas,i3c.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/i3c/renesas,i3c.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas RZ/G3S and RZ/G3E I3C Bus Interface
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maintainers:
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- Wolfram Sang <wsa+renesas@sang-engineering.com>
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- Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
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properties:
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compatible:
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items:
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- enum:
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- renesas,r9a08g045-i3c # RZ/G3S
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- renesas,r9a09g047-i3c # RZ/G3E
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reg:
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maxItems: 1
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interrupts:
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items:
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- description: Non-recoverable internal error interrupt
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- description: Normal transfer error interrupt
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- description: Normal transfer abort interrupt
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- description: Normal response status buffer full interrupt
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- description: Normal command buffer empty interrupt
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- description: Normal IBI status buffer full interrupt
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- description: Normal Rx data buffer full interrupt
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- description: Normal Tx data buffer empty interrupt
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- description: Normal receive status buffer full interrupt
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- description: START condition detection interrupt
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- description: STOP condition detection interrupt
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- description: Transmit end interrupt
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- description: NACK detection interrupt
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- description: Arbitration lost interrupt
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- description: Timeout detection interrupt
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- description: Wake-up condition detection interrupt
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- description: HDR Exit Pattern detection interrupt
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minItems: 16
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interrupt-names:
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items:
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- const: ierr
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- const: terr
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- const: abort
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- const: resp
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- const: cmd
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- const: ibi
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- const: rx
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- const: tx
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- const: rcv
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- const: st
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- const: sp
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- const: tend
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- const: nack
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- const: al
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- const: tmo
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- const: wu
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- const: exit
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minItems: 16
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clocks:
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items:
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- description: APB bus clock
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- description: transfer clock
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- description: SFRs clock
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minItems: 2
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clock-names:
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items:
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- const: pclk
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- const: tclk
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- const: pclkrw
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minItems: 2
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power-domains:
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maxItems: 1
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resets:
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items:
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- description: Reset signal
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- description: APB interface reset signal/SCAN reset signal
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reset-names:
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items:
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- const: presetn
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- const: tresetn
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required:
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- compatible
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- reg
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- interrupts
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- interrupt-names
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- clock-names
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- clocks
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- power-domains
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- resets
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- reset-names
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allOf:
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- $ref: i3c.yaml#
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- if:
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properties:
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compatible:
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contains:
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const: renesas,r9a08g045-i3c
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then:
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properties:
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clocks:
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maxItems: 2
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clock-names:
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maxItems: 2
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interrupts:
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minItems: 17
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interrupt-names:
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minItems: 17
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- if:
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properties:
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compatible:
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contains:
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const: renesas,r9a09g047-i3c
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then:
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properties:
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clocks:
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minItems: 3
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clock-names:
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minItems: 3
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interrupts:
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maxItems: 16
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interrupt-names:
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maxItems: 16
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/r9a08g045-cpg.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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i3c@1005b000 {
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compatible = "renesas,r9a08g045-i3c";
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reg = <0x1005b000 0x1000>;
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clocks = <&cpg CPG_MOD R9A08G045_I3C_PCLK>,
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<&cpg CPG_MOD R9A08G045_I3C_TCLK>;
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clock-names = "pclk", "tclk";
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interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 294 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 295 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 296 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 297 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 298 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 299 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "ierr", "terr", "abort", "resp",
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"cmd", "ibi", "rx", "tx", "rcv",
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"st", "sp", "tend", "nack",
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"al", "tmo", "wu", "exit";
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resets = <&cpg R9A08G045_I3C_PRESETN>,
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<&cpg R9A08G045_I3C_TRESETN>;
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reset-names = "presetn", "tresetn";
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power-domains = <&cpg>;
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#address-cells = <3>;
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#size-cells = <0>;
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};
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...
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