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drm/amd/display: Move the memory allocation out of dcn21_validate_bandwidth_fp().

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dcn21_validate_bandwidth_fp() is invoked while FPU access has been
enabled. FPU access requires disabling preemption even on PREEMPT_RT.
It is not possible to allocate memory with disabled preemption even with
GFP_ATOMIC on PREEMPT_RT.

Move the memory allocation before FPU access is enabled.

Link: https://bugzilla.kernel.org/show_bug.cgi?id=217928
Acked-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Sebastian Andrzej Siewior
2023-09-21 16:15:15 +02:00
committed by Alex Deucher
parent 80364500c0
commit 941e8036a4
3 changed files with 13 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
drivers/gpu/drm/amd/display/dc/dcn21/dcn21_resource.c
View File

@@ -953,9 +953,17 @@ static bool dcn21_validate_bandwidth(struct dc *dc, struct dc_state *context,
bool fast_validate)
{
bool voltage_supported;
display_e2e_pipe_params_st *pipes;
pipes = kcalloc(dc->res_pool->pipe_count, sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
if (!pipes)
return false;
DC_FP_START();
voltage_supported = dcn21_validate_bandwidth_fp(dc, context, fast_validate);
voltage_supported = dcn21_validate_bandwidth_fp(dc, context, fast_validate, pipes);
DC_FP_END();
kfree(pipes);
return voltage_supported;
}

7
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
View File

@@ -2218,9 +2218,8 @@ static void dcn21_calculate_wm(struct dc *dc, struct dc_state *context,
&context->bw_ctx.dml, pipes, pipe_cnt);
}
bool dcn21_validate_bandwidth_fp(struct dc *dc,
struct dc_state *context,
bool fast_validate)
bool dcn21_validate_bandwidth_fp(struct dc *dc, struct dc_state *context,
bool fast_validate, display_e2e_pipe_params_st *pipes)
{
bool out = false;
@@ -2229,7 +2228,6 @@ bool dcn21_validate_bandwidth_fp(struct dc *dc,
int vlevel = 0;
int pipe_split_from[MAX_PIPES];
int pipe_cnt = 0;
display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_ATOMIC);
DC_LOGGER_INIT(dc->ctx->logger);
BW_VAL_TRACE_COUNT();
@@ -2269,7 +2267,6 @@ bool dcn21_validate_bandwidth_fp(struct dc *dc,
out = false;
validate_out:
kfree(pipes);
BW_VAL_TRACE_FINISH();

5
drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.h
View File

@@ -77,9 +77,8 @@ int dcn21_populate_dml_pipes_from_context(struct dc *dc,
struct dc_state *context,
display_e2e_pipe_params_st *pipes,
bool fast_validate);
bool dcn21_validate_bandwidth_fp(struct dc *dc,
struct dc_state *context,
bool fast_validate);
bool dcn21_validate_bandwidth_fp(struct dc *dc, struct dc_state *context, bool
fast_validate, display_e2e_pipe_params_st *pipes);
void dcn21_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params);
void dcn21_clk_mgr_set_bw_params_wm_table(struct clk_bw_params *bw_params);